From owner-p4-projects@FreeBSD.ORG Fri May 2 17:58:40 2003 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id 4459337B404; Fri, 2 May 2003 17:58:40 -0700 (PDT) Delivered-To: perforce@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id EF1E937B401 for ; Fri, 2 May 2003 17:58:39 -0700 (PDT) Received: from repoman.freebsd.org (repoman.freebsd.org [216.136.204.115]) by mx1.FreeBSD.org (Postfix) with ESMTP id 8437B43FAF for ; Fri, 2 May 2003 17:58:39 -0700 (PDT) (envelope-from jmallett@freebsd.org) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.12.6/8.12.6) with ESMTP id h430wd0U065200 for ; Fri, 2 May 2003 17:58:39 -0700 (PDT) (envelope-from jmallett@freebsd.org) Received: (from perforce@localhost) by repoman.freebsd.org (8.12.6/8.12.6/Submit) id h430wcNT065197 for perforce@freebsd.org; Fri, 2 May 2003 17:58:38 -0700 (PDT) Date: Fri, 2 May 2003 17:58:38 -0700 (PDT) Message-Id: <200305030058.h430wcNT065197@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: perforce set sender to jmallett@freebsd.org using -f From: Juli Mallett To: Perforce Change Reviews Subject: PERFORCE change 30428 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 03 May 2003 00:58:41 -0000 http://perforce.freebsd.org/chv.cgi?CH=30428 Change 30428 by jmallett@jmallett_dalek on 2003/05/02 17:58:14 Make it possible to build with invariants+witness+so-on. This means that now everything has warnings, yay! Time to split up locore.h into cpufunc.h and other places where it should be. Yay for NetBSD grottiness, yay! Affected files ... .. //depot/projects/mips/sys/mips/include/cpu.h#10 edit .. //depot/projects/mips/sys/mips/include/cpufunc.h#7 edit .. //depot/projects/mips/sys/mips/mips/cache.c#3 edit .. //depot/projects/mips/sys/mips/mips/machdep.c#19 edit Differences ... ==== //depot/projects/mips/sys/mips/include/cpu.h#10 (text+ko) ==== @@ -53,6 +53,7 @@ #define CLKF_INTR(framep) (0) #define TRAPF_PC(tframe) ((tframe)->tf_regs[TF_EPC]) +#define TRAPF_USERMODE(tframe) ((tframe)->tf_regs[TF_SR] & MIPS_SR_KSU_USER) #define cpu_getstack(p) (0) #define cpu_setstack(p, sp) (0) ==== //depot/projects/mips/sys/mips/include/cpufunc.h#7 (text+ko) ==== @@ -31,6 +31,19 @@ #ifdef _KERNEL #include +#include + +static __inline register_t +intr_disable(void) +{ + register_t s; + + s = mips_cp0_status_read(); + mips_cp0_status_write((s = mips_cp0_status_read()) & ~MIPS_SR_IE); + return (s); +} + +#define intr_restore(s) mips_cp0_status_write((s)) static __inline void mips_break(void) ==== //depot/projects/mips/sys/mips/mips/cache.c#3 (text+ko) ==== @@ -226,7 +226,7 @@ { int csizebase = MIPS3_CONFIG_C_DEFBASE; - KASSERT(PAGE_SIZE != 0, "sane page size"); + KASSERT(PAGE_SIZE != 0, ("sane page size")); /* * Configure primary caches. @@ -383,7 +383,7 @@ */ if (MIPS_PRID_IMPL(cpu_id) == MIPS_R4600 && MIPS_PRID_REV_MAJ(cpu_id) == 1) { - KASSERT(mips_pdcache_line_size == 32, "line size 32"); + KASSERT(mips_pdcache_line_size == 32, ("line size 32")); mips_cache_ops.mco_pdcache_wbinv_range = r4600v1_pdcache_wbinv_range_32; mips_cache_ops.mco_pdcache_inv_range = @@ -392,7 +392,7 @@ r4600v1_pdcache_wb_range_32; } else if (MIPS_PRID_IMPL(cpu_id) == MIPS_R4600 && MIPS_PRID_REV_MAJ(cpu_id) == 2) { - KASSERT(mips_pdcache_line_size == 32, "line size 32"); + KASSERT(mips_pdcache_line_size == 32, ("line size 32")); mips_cache_ops.mco_pdcache_wbinv_range = r4600v2_pdcache_wbinv_range_32; mips_cache_ops.mco_pdcache_inv_range = @@ -406,7 +406,7 @@ */ if (MIPS_PRID_IMPL(cpu_id) == MIPS_R4100 && MIPS_PRID_REV_MAJ(cpu_id) == 8) { - KASSERT(mips_pdcache_line_size == 16, "line size 16"); + KASSERT(mips_pdcache_line_size == 16, ("line size 16")); mips_cache_ops.mco_pdcache_wbinv_range = vr4131v1_pdcache_wbinv_range_16; } @@ -422,12 +422,12 @@ * Compute the "way mask" for each cache. */ if (mips_picache_size) { - KASSERT(mips_picache_ways != 0, "sane ways"); + KASSERT(mips_picache_ways != 0, ("sane ways")); mips_picache_way_size = (mips_picache_size / mips_picache_ways); mips_picache_way_mask = mips_picache_way_size - 1; } if (mips_pdcache_size) { - KASSERT(mips_pdcache_ways != 0, "sane ways"); + KASSERT(mips_pdcache_ways != 0, ("sane ways")); mips_pdcache_way_size = (mips_pdcache_size / mips_pdcache_ways); mips_pdcache_way_mask = mips_pdcache_way_size - 1; } @@ -536,7 +536,7 @@ * Compute the "way mask" for each secondary cache. */ if (mips_sdcache_size) { - KASSERT(mips_sdcache_ways != 0, "sane ways"); + KASSERT(mips_sdcache_ways != 0, ("sane ways")); mips_sdcache_way_size = (mips_sdcache_size / mips_sdcache_ways); mips_sdcache_way_mask = mips_sdcache_way_size - 1; } ==== //depot/projects/mips/sys/mips/mips/machdep.c#19 (text+ko) ==== @@ -552,6 +552,9 @@ /* MIPS32/MIPS64 interrupt exception handler */ extern char mips64_intr[], mips64_intrEnd[]; + /* XXX I want ARCS to be my friend */ + return; + /* * Copy down exception vector code. */ @@ -826,10 +829,10 @@ "dmesg lines.\n", label); } - KASSERT(mips_picache_ways < nwaynames, "picache ways < nwaynames"); - KASSERT(mips_pdcache_ways < nwaynames, "pdcache ways < nwaynames"); - KASSERT(mips_sicache_ways < nwaynames, "sicache ways < nwaynames"); - KASSERT(mips_sdcache_ways < nwaynames, "sdcache ways < nwaynames"); + KASSERT(mips_picache_ways < nwaynames, ("picache ways < nwaynames")); + KASSERT(mips_pdcache_ways < nwaynames, ("pdcache ways < nwaynames")); + KASSERT(mips_sicache_ways < nwaynames, ("sicache ways < nwaynames")); + KASSERT(mips_sdcache_ways < nwaynames, ("sdcache ways < nwaynames")); switch (cpu_arch) { case CPU_ARCH_MIPS3: