From owner-freebsd-arm@FreeBSD.ORG Wed Nov 20 16:00:01 2013 Return-Path: Delivered-To: freebsd-arm@smarthost.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 92C19D4A for ; Wed, 20 Nov 2013 16:00:01 +0000 (UTC) Received: from freefall.freebsd.org (freefall.freebsd.org [IPv6:2001:1900:2254:206c::16:87]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.freebsd.org (Postfix) with ESMTPS id 6902E2559 for ; Wed, 20 Nov 2013 16:00:01 +0000 (UTC) Received: from freefall.freebsd.org (localhost [127.0.0.1]) by freefall.freebsd.org (8.14.7/8.14.7) with ESMTP id rAKG01G3077281 for ; Wed, 20 Nov 2013 16:00:01 GMT (envelope-from gnats@freefall.freebsd.org) Received: (from gnats@localhost) by freefall.freebsd.org (8.14.7/8.14.7/Submit) id rAKG01Hn077279; Wed, 20 Nov 2013 16:00:01 GMT (envelope-from gnats) Date: Wed, 20 Nov 2013 16:00:01 GMT Message-Id: <201311201600.rAKG01Hn077279@freefall.freebsd.org> To: freebsd-arm@FreeBSD.org Cc: From: dfilter@FreeBSD.ORG (dfilter service) Subject: Re: arm/183740: commit references a PR X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.16 Precedence: list Reply-To: dfilter service List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 20 Nov 2013 16:00:01 -0000 The following reply was made to PR arm/183740; it has been noted by GNATS. From: dfilter@FreeBSD.ORG (dfilter service) To: bug-followup@FreeBSD.org Cc: Subject: Re: arm/183740: commit references a PR Date: Wed, 20 Nov 2013 15:53:57 +0000 (UTC) Author: ian Date: Wed Nov 20 15:53:50 2013 New Revision: 258392 URL: http://svnweb.freebsd.org/changeset/base/258392 Log: Call cpu_setup() immediately after the page tables are installed. This enables data cache and other chip-specific features. It was previously done via an early SYSINIT, but it was being done after pmap and vm setup, and those setups need to use mutexes. On some modern ARM platforms, the ldrex/strex instructions that implement mutexes require the data cache to be enabled. A nice side effect of enabling caching earlier is that it eliminates the multi-second pause that used to happen early in boot while physical memory and pmap and vm were being set up. On boards with 1 GB or more of ram this pause was very noticible, sometimes 5-6 seconds. PR: arm/183740 Modified: head/sys/arm/arm/machdep.c Modified: head/sys/arm/arm/machdep.c ============================================================================== --- head/sys/arm/arm/machdep.c Wed Nov 20 13:22:22 2013 (r258391) +++ head/sys/arm/arm/machdep.c Wed Nov 20 15:53:50 2013 (r258392) @@ -361,7 +361,6 @@ cpu_startup(void *dummy) #endif #endif - cpu_setup(""); identify_arm_cpu(); printf("real memory = %ju (%ju MB)\n", (uintmax_t)ptoa(physmem), @@ -1431,6 +1430,12 @@ initarm(struct arm_boot_params *abp) cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)); /* + * Now that proper page tables are installed, call cpu_setup() to enable + * instruction and data caches and other chip-specific features. + */ + cpu_setup(""); + + /* * Only after the SOC registers block is mapped we can perform device * tree fixups, as they may attempt to read parameters from hardware. */ _______________________________________________ svn-src-all@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to "svn-src-all-unsubscribe@freebsd.org"