Date: Fri, 13 Sep 1996 20:06:34 -0700 (PDT) From: "Rodney W. Grimes" <rgrimes@GndRsh.aac.dev.com> To: erich@uruk.org Cc: smp@csn.net, smp@freebsd.org, peter@spinner.dialix.com Subject: Re: writing new apic_startup Message-ID: <199609140306.UAA01724@GndRsh.aac.dev.com> In-Reply-To: <199609140231.TAA16417@uruk.org> from "erich@uruk.org" at "Sep 13, 96 07:31:46 pm"
next in thread | previous in thread | raw e-mail | index | archive | help
> > "Rodney W. Grimes" <rgrimes@GndRsh.aac.dev.com> writes: > > > > Failing that does anyone see any reason why I shouldn't use the APIC > > > timer? Is it currently used on the boot CPU for anything else? > > > > The very reason Intel added a timer to the APIC was because of the need to > > do these timings during SMP initilization. Please do write your code to use > > the APIC timer. > > I'd *highly* suggest that anybody doing this kind of stuff look at the > Pentium eratta. I remember at least one bug in some versions about the > APIC timer being somewhat off in some circumstances. The only reference I find in my old May 1995 Pentium Errata book (242480-004) with respect to this is Specification Clarification number 5. Basically timer interval 0 is of 1 PIC clock duration, where as the other timer intervals are of ``divisor'' length. A future version of the processor (this book only covers upto stepping C5 == CPUID xx5) will totally eliminate interval zero (the timer will count down 5,4,3,2,1,5,4,3,2,1) and the interrupt will occur at the end of interval 1. So those writing this code should infact read this errata, I will fax it to whomever is undertaking this task. If Erich knows of some other errata about the APIC timer I have over looked I'll obtain a later spec update and send that out as well. -- Rod Grimes rgrimes@gndrsh.aac.dev.com Accurate Automation Company Reliable computers for FreeBSD
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?199609140306.UAA01724>