From owner-freebsd-arm@FreeBSD.ORG Thu Aug 23 23:36:46 2012 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 5376E106564A; Thu, 23 Aug 2012 23:36:46 +0000 (UTC) (envelope-from adrian.chadd@gmail.com) Received: from mail-pb0-f54.google.com (mail-pb0-f54.google.com [209.85.160.54]) by mx1.freebsd.org (Postfix) with ESMTP id 17DD18FC15; Thu, 23 Aug 2012 23:36:45 +0000 (UTC) Received: by pbbrp2 with SMTP id rp2so2415467pbb.13 for ; Thu, 23 Aug 2012 16:36:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type; bh=ZqDIjzxMgU3yZwSHpcg2vnW8k3VCuuGcmucl0nHa5xc=; b=qFD3SNi7TjXoHyZyjZc9Cgz9jPt4O0ldrMYgS8HZgp7xzg9tLQju4GahEViI36qO7G 69jHiCDwYe7Unv2VK5NwuH8/LSHXHoH7+cQYP30Oq/Dy7aUEd5k07rptR1hfkbTbXXsp dp5tVjalA9IKe87/jGIPFa4op6MpTriSAw93In2RDvlV5a29SSzxJ6NEXxz+EQB8QQhH CEh2GWHctCICw98iocvHxn0xjQYiRupsd1hVXuKZ9a+V5dEZfUjGGhdinEC+OjmH9Idi 2x3D/BEge6egfP/6T8/ziCRcpdiu7a2IpNOFwMVrzTq6XF7gcz/OQ/p9M2YZvfAbgbSZ qSPA== MIME-Version: 1.0 Received: by 10.68.136.40 with SMTP id px8mr8215347pbb.153.1345765005641; Thu, 23 Aug 2012 16:36:45 -0700 (PDT) Sender: adrian.chadd@gmail.com Received: by 10.68.36.106 with HTTP; Thu, 23 Aug 2012 16:36:45 -0700 (PDT) In-Reply-To: <1345764428.27688.591.camel@revolution.hippie.lan> References: <1345757300.27688.535.camel@revolution.hippie.lan> <1345764428.27688.591.camel@revolution.hippie.lan> Date: Thu, 23 Aug 2012 16:36:45 -0700 X-Google-Sender-Auth: 8N9-uFx59Shvyoz92HPvSALf2iE Message-ID: From: Adrian Chadd To: Ian Lepore Content-Type: text/plain; charset=ISO-8859-1 Cc: freebsd-arm@freebsd.org, freebsd-mips@freebsd.org, freebsd-arch@freebsd.org Subject: Re: Partial cacheline flush problems on ARM and MIPS X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 23 Aug 2012 23:36:46 -0000 Right, that's what Linux does for ARM/MIPS. It just sets the minimum allocation size to be cache line sized. That way they didn't have to fix their USB and network stack code. .. or, we could fix the USB stack code by saying that anything being used as a DMA buffer needs to be minimum cache line size (which can be determined at run time if appropriate) and make the minimum allocation that. Then either it uses a separate allocation for each buffer or it allocates one big set of buffers and chops them up in at least "cache line size" bits. That reminds me, I should do that to the descriptor allocation in the Atheros driver - ie, round up the descriptor allocation size to a multiple of a cache line. That way DMAs don't conflict with the next DMAed buffer.. Adrian