Date: Thu, 5 Dec 2002 17:31:21 +0100 From: "Oliver Blasnik" <oliver.blasnik@de.tiscali.com> To: "Thomas Moestl" <tmoestl@gmx.net> Cc: "Jake Burkholder" <jake@locore.ca>, <freebsd-sparc@FreeBSD.ORG> Subject: Re: pci quad hme ethernet card Message-ID: <004201c29c7b$bf00b400$1d0a310a@de.tiscali.com> References: <20021203124613.L35729@locore.ca> <010d01c29b74$65d3b4c0$2100a8c0@xpath1000> <20021204140045.S35729@locore.ca> <005b01c29c42$93cc75a0$2100a8c0@xpath1000> <20021205121437.GA305@crow.dom2ip.de> <009f01c29c5f$a09942a0$1d0a310a@de.tiscali.com> <20021205151924.GA305@crow.dom2ip.de> <000c01c29c76$4b5faab0$1d0a310a@de.tiscali.com> <20021205155434.GB305@crow.dom2ip.de>
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Hi,
> > > Hummm, that looks quite normal, the ATA controller should get
> > > interrupt 2 and the hmes 3, 4, 1 and 2.
> > That was like _before_ I updated to the latest sources. Funny...
> > Not.
> Which interrupts do they get assigned now?
hme0: [...] mem 0x2800000-0x2807fff irq 0 at device 0.1 on pci4
hme1: [...] mem 0x4800000-0x4807fff irq 1 at device 1.1 on pci4
hme2: [...] mem 0x6800000-0x6807fff irq 2 at device 2.1 on pci4
hme3: [...] mem 0x8800000-0x8807fff irq 3 at device 3.1 on pci4
Hum... That doesn look like your "3, 4, 1 and 2". Are you sure about?
The output is very interesting...
Func01 (hme chip) @ INTB gets 0, 1, 2, 3.
Func00 (bridge) @ INTA gets 3, 0, 1, 2 -> looks like (INTB+1)&3.
At least the 00 is near of that you said: 3, _4_, 1, 2 (is it AND 3?),
but who cares of the bridge? Isn't it a transparent one?
Ok, then the "interesting parts" of the dmesg:
*---------* new debugging START
pcib0: <U2P UPA-PCI bridge> on nexus0
pcib0: Sabre, impl 0, version 0, ign 7c0 DVMA map: 0xc0000000 to 0xdfffffff
orb_callback: pintr 1, intr 3, HI_DEV.phys_hi: 14
orb_callback: pintr 1, intr 1, HI_DEV.phys_hi: 0
orb_callback: pintr 1, intr 4, HI_DEV.phys_hi: 15
orb_callback: pintr 2, intr 2, HI_DEV.phys_hi: 0
orb_callback: pintr 2, intr 1, HI_DEV.phys_hi: 15
orb_callback: pintr 1, intr 2, HI_DEV.phys_hi: 1
orb_callback: pintr 2, intr 1, HI_DEV.phys_hi: 15
orb_callback: pintr 2, intr 3, HI_DEV.phys_hi: 1
orb_callback: pintr 3, intr 2, HI_DEV.phys_hi: 15
orb_callback: pintr 1, intr 3, HI_DEV.phys_hi: 2
orb_callback: pintr 3, intr 2, HI_DEV.phys_hi: 15
orb_callback: pintr 2, intr 4, HI_DEV.phys_hi: 2
orb_callback: pintr 4, intr 3, HI_DEV.phys_hi: 15
orb_callback: pintr 1, intr 4, HI_DEV.phys_hi: 3
orb_callback: pintr 4, intr 3, HI_DEV.phys_hi: 15
orb_callback: pintr 2, intr 1, HI_DEV.phys_hi: 3
orb_callback: pintr 1, intr 4, HI_DEV.phys_hi: 15
*---------* new debugging END
*---------* detection of the qfe START
pcib3: <PCI-PCI bridge> at device 15.0 on pci3
pcib3: secondary bus 4
pcib3: subordinate bus 4
pcib3: I/O decode 0x1000-0xfff
pcib3: memory decode 0x100000-0x88fffff
pcib3: prefetched decode 0xfff00000-0xfffff
pci4: <PCI bus> on pcib3
pci4: physical bus=4
map[10]: type 1, range 32, base 01000000, size 24, memory disabled
map[14]: type 1, range 32, base 02000000, size 23, enabled
found-> vendor=0x108e, dev=0x1000, revid=0x01
bus=4, slot=0, func=0
class=06-80-00, hdrtype=0x00, mfdev=1
cmdreg=0x0000, statreg=0x0280, cachelnsz=0 (dwords)
lattimer=0x52 (2460 ns), mingnt=0x0a (2500 ns), maxlat=0x19 (6250
ns)
intpin=a, irq=3
map[10]: type 1, range 32, base 02800000, size 15, memory disabled
found-> vendor=0x108e, dev=0x1001, revid=0x01
bus=4, slot=0, func=1
class=02-00-00, hdrtype=0x00, mfdev=1
cmdreg=0x0000, statreg=0x0280, cachelnsz=0 (dwords)
lattimer=0x52 (2460 ns), mingnt=0x0a (2500 ns), maxlat=0x05 (1250
ns)
intpin=b, irq=0
map[10]: type 1, range 32, base 03000000, size 24, memory disabled
map[14]: type 1, range 32, base 04000000, size 23, enabled
found-> vendor=0x108e, dev=0x1000, revid=0x01
bus=4, slot=1, func=0
class=06-80-00, hdrtype=0x00, mfdev=1
cmdreg=0x0000, statreg=0x0280, cachelnsz=0 (dwords)
lattimer=0x52 (2460 ns), mingnt=0x0a (2500 ns), maxlat=0x19 (6250
ns)
intpin=a, irq=0
map[10]: type 1, range 32, base 04800000, size 15, memory disabled
found-> vendor=0x108e, dev=0x1001, revid=0x01
bus=4, slot=1, func=1
class=02-00-00, hdrtype=0x00, mfdev=1
cmdreg=0x0000, statreg=0x0280, cachelnsz=0 (dwords)
lattimer=0x52 (2460 ns), mingnt=0x0a (2500 ns), maxlat=0x05 (1250
ns)
intpin=b, irq=1
map[10]: type 1, range 32, base 05000000, size 24, memory disabled
map[14]: type 1, range 32, base 06000000, size 23, enabled
found-> vendor=0x108e, dev=0x1000, revid=0x01
bus=4, slot=2, func=0
class=06-80-00, hdrtype=0x00, mfdev=1
cmdreg=0x0000, statreg=0x0280, cachelnsz=0 (dwords)
lattimer=0x52 (2460 ns), mingnt=0x0a (2500 ns), maxlat=0x19 (6250
ns)
intpin=a, irq=1
map[10]: type 1, range 32, base 06800000, size 15, memory disabled
found-> vendor=0x108e, dev=0x1001, revid=0x01
bus=4, slot=2, func=1
class=02-00-00, hdrtype=0x00, mfdev=1
cmdreg=0x0000, statreg=0x0280, cachelnsz=0 (dwords)
lattimer=0x52 (2460 ns), mingnt=0x0a (2500 ns), maxlat=0x05 (1250
ns)
intpin=b, irq=2
map[10]: type 1, range 32, base 07000000, size 24, memory disabled
map[14]: type 1, range 32, base 08000000, size 23, enabled
found-> vendor=0x108e, dev=0x1000, revid=0x01
bus=4, slot=3, func=0
class=06-80-00, hdrtype=0x00, mfdev=1
cmdreg=0x0000, statreg=0x0280, cachelnsz=0 (dwords)
lattimer=0x52 (2460 ns), mingnt=0x0a (2500 ns), maxlat=0x19 (6250
ns)
intpin=a, irq=2
map[10]: type 1, range 32, base 08800000, size 15, memory disabled
found-> vendor=0x108e, dev=0x1001, revid=0x01
bus=4, slot=3, func=1
class=02-00-00, hdrtype=0x00, mfdev=1
cmdreg=0x0000, statreg=0x0280, cachelnsz=0 (dwords)
lattimer=0x52 (2460 ns), mingnt=0x0a (2500 ns), maxlat=0x05 (1250
ns)
intpin=b, irq=3
*---------* detection of the qfe END
> - Thomas
HTH, Oliver
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