From owner-freebsd-stable@FreeBSD.ORG Sat May 23 21:10:34 2015 Return-Path: Delivered-To: freebsd-stable@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 8D5DA3E5; Sat, 23 May 2015 21:10:34 +0000 (UTC) Received: from mail-la0-x236.google.com (mail-la0-x236.google.com [IPv6:2a00:1450:4010:c03::236]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (Client CN "smtp.gmail.com", Issuer "Google Internet Authority G2" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 0EAAF1E5B; Sat, 23 May 2015 21:10:34 +0000 (UTC) Received: by lami4 with SMTP id i4so31383570lam.0; Sat, 23 May 2015 14:10:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=La4H8iuTENAoCf1T07Sub2aJmGgRyFXmHqCsQf4wVro=; b=XRL+eRltv82NjC1FBF7LN+ZzukQUJE6/jUxRB1lzg5hkcBDme7bfOt0HYyRZD9qA2h fXNRMJziBHKe47u4nsaFTR5W7Ff73VQADvsUfxZX0t9a/ziyfXRSUMguYjr1g+s0PxOL tfFnVSD7DbAnMX9KK7e6mfP+Ivw/H4DjKzTvcZnyt/khy6J42bmvxNbKs/07rB2U4Gep G5xVWAg917uw9lxRtYIm0UbevABDdQo1QJkszk050J5J0DTjCWxx6bqZoQdfCyz7ZaB9 woMLOnkH8IbSdTnMT445T8KRA1QyqsMidscvxOJp5sd7QFTNfPXuywtYcfY72izDtEIo fLDg== MIME-Version: 1.0 X-Received: by 10.152.27.105 with SMTP id s9mr11860439lag.86.1432415432087; Sat, 23 May 2015 14:10:32 -0700 (PDT) Received: by 10.152.137.193 with HTTP; Sat, 23 May 2015 14:10:32 -0700 (PDT) In-Reply-To: References: <555C71C8.4080007@gmx.com> <555EDBBB.4090107@gmx.com> <20150522104213.4e083225@nonamehost.local> <20150523014640.K7173@sola.nimnet.asn.au> <20150523163014.U7173@sola.nimnet.asn.au> <20150523234646.R7173@sola.nimnet.asn.au> <20150524010831.W7173@sola.nimnet.asn.au> Date: Sun, 24 May 2015 00:10:32 +0300 Message-ID: Subject: Re: CPU frequency doesn't drop below 1200MHz (like it used to) From: Kimmo Paasiala To: Adrian Chadd Cc: Ian Smith , "freebsd-stable@freebsd.org" Content-Type: text/plain; charset=UTF-8 X-BeenThere: freebsd-stable@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Production branch of FreeBSD source code List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 23 May 2015 21:10:34 -0000 On Sat, May 23, 2015 at 10:41 PM, Adrian Chadd wrote: > Frequency control may not be relevant on that platform. > > Try installing the intel-pcm package; then > > # kldload cpuctl > # pcm.x 1 > > Then paste some of that in here. Let's see if the CPU is idling some other way. > > > > -adrian Five iterations one every second: Script started on Sun May 24 00:07:18 2015 command: sudo pcm.x 1 -i=5 Intel(r) Performance Counter Monitor V2.8 (2014-12-18 12:52:39 +0100 ID=ba39a89) Copyright (c) 2009-2014 Intel Corporation Number of physical cores: 1 Number of logical cores: 4 Number of online logical cores: 4 Threads (logical cores) per physical core: 4 Num sockets: 1 Physical cores per socket: 1 Core PMU (perfmon) version: 3 Number of core PMU generic (programmable) counters: 2 Width of generic (programmable) counters: 40 bits Number of core PMU fixed counters: 3 Width of fixed counters: 40 bits Nominal core frequency: 1660000000 Hz Delay: 1 Detected Intel(R) Atom(TM) CPU D510 @ 1.66GHz "Intel(r) microarchitecture codename Atom(tm)" EXEC : instructions per nominal CPU cycle IPC : instructions per CPU cycle FREQ : relation to nominal CPU frequency='unhalted clock ticks'/'invariant timer ticks' (includes Intel Turbo Boost) L2MISS: L2 cache misses L2HIT : L2 cache hit ratio (0.00-1.00) TEMP : Temperature reading in 1 degree Celsius relative to the TjMax temperature (thermal headroom): 0 corresponds to the max temperature Core (SKT) | EXEC | IPC | FREQ | L2MISS | L2HIT | TEMP 0 0 0.00 0.19 0.00 5513 0.85 89 1 0 0.00 0.37 0.00 2676 0.84 89 2 0 0.00 0.39 0.01 21 K 0.83 N/A 3 0 0.00 0.28 0.00 4731 0.64 N/A ----------------------------------------------------------------------------------------------------------------------------- TOTAL * 0.00 0.33 0.00 34 K 0.82 N/A Instructions retired: 6666 K ; Active cycles: 20 M ; Time (TSC): 1765 Mticks ; C0 (active,non-halted) core residency: 0.28 % C1 core residency: 99.72 %; C2 package residency: 0.00 %; C4 package residency: 0.00 %; C6 package residency: 0.00 %; PHYSICAL CORE IPC : 1.33 => corresponds to 66.42 % utilization for cores in active state Instructions per nominal CPU cycle: 0.00 => corresponds to 0.19 % core utilization over time interval ---------------------------------------------------------------------------------------------- EXEC : instructions per nominal CPU cycle IPC : instructions per CPU cycle FREQ : relation to nominal CPU frequency='unhalted clock ticks'/'invariant timer ticks' (includes Intel Turbo Boost) L2MISS: L2 cache misses L2HIT : L2 cache hit ratio (0.00-1.00) TEMP : Temperature reading in 1 degree Celsius relative to the TjMax temperature (thermal headroom): 0 corresponds to the max temperature Core (SKT) | EXEC | IPC | FREQ | L2MISS | L2HIT | TEMP 0 0 0.00 0.19 0.00 6296 0.82 89 1 0 0.00 0.35 0.00 12 K 0.81 89 2 0 0.00 0.44 0.00 6378 0.84 N/A 3 0 0.00 0.24 0.00 3846 0.86 N/A ----------------------------------------------------------------------------------------------------------------------------- TOTAL * 0.00 0.34 0.00 29 K 0.83 N/A Instructions retired: 6646 K ; Active cycles: 19 M ; Time (TSC): 1766 Mticks ; C0 (active,non-halted) core residency: 0.28 % C1 core residency: 99.72 %; C2 package residency: 0.00 %; C4 package residency: 0.00 %; C6 package residency: 0.00 %; PHYSICAL CORE IPC : 1.34 => corresponds to 67.19 % utilization for cores in active state Instructions per nominal CPU cycle: 0.00 => corresponds to 0.19 % core utilization over time interval ---------------------------------------------------------------------------------------------- EXEC : instructions per nominal CPU cycle IPC : instructions per CPU cycle FREQ : relation to nominal CPU frequency='unhalted clock ticks'/'invariant timer ticks' (includes Intel Turbo Boost) L2MISS: L2 cache misses L2HIT : L2 cache hit ratio (0.00-1.00) TEMP : Temperature reading in 1 degree Celsius relative to the TjMax temperature (thermal headroom): 0 corresponds to the max temperature Core (SKT) | EXEC | IPC | FREQ | L2MISS | L2HIT | TEMP 0 0 0.00 0.25 0.00 12 K 0.74 89 1 0 0.00 0.42 0.00 3166 0.94 89 2 0 0.00 0.19 0.00 4869 0.68 94 3 0 0.00 0.36 0.00 13 K 0.81 94 ----------------------------------------------------------------------------------------------------------------------------- TOTAL * 0.00 0.34 0.00 33 K 0.82 N/A Instructions retired: 8041 K ; Active cycles: 23 M ; Time (TSC): 1755 Mticks ; C0 (active,non-halted) core residency: 0.34 % C1 core residency: 99.66 %; C2 package residency: 0.00 %; C4 package residency: 0.00 %; C6 package residency: 0.00 %; PHYSICAL CORE IPC : 1.36 => corresponds to 67.89 % utilization for cores in active state Instructions per nominal CPU cycle: 0.00 => corresponds to 0.23 % core utilization over time interval ---------------------------------------------------------------------------------------------- EXEC : instructions per nominal CPU cycle IPC : instructions per CPU cycle FREQ : relation to nominal CPU frequency='unhalted clock ticks'/'invariant timer ticks' (includes Intel Turbo Boost) L2MISS: L2 cache misses L2HIT : L2 cache hit ratio (0.00-1.00) TEMP : Temperature reading in 1 degree Celsius relative to the TjMax temperature (thermal headroom): 0 corresponds to the max temperature Core (SKT) | EXEC | IPC | FREQ | L2MISS | L2HIT | TEMP 0 0 0.00 0.20 0.00 4436 0.85 89 1 0 0.00 0.30 0.00 3244 0.77 89 2 0 0.00 0.41 0.01 4260 0.93 N/A 3 0 0.00 0.35 0.00 11 K 0.83 N/A ----------------------------------------------------------------------------------------------------------------------------- TOTAL * 0.00 0.34 0.00 23 K 0.86 N/A Instructions retired: 7227 K ; Active cycles: 21 M ; Time (TSC): 1765 Mticks ; C0 (active,non-halted) core residency: 0.30 % C1 core residency: 99.70 %; C2 package residency: 0.00 %; C4 package residency: 0.00 %; C6 package residency: 0.00 %; PHYSICAL CORE IPC : 1.37 => corresponds to 68.70 % utilization for cores in active state Instructions per nominal CPU cycle: 0.00 => corresponds to 0.20 % core utilization over time interval ---------------------------------------------------------------------------------------------- EXEC : instructions per nominal CPU cycle IPC : instructions per CPU cycle FREQ : relation to nominal CPU frequency='unhalted clock ticks'/'invariant timer ticks' (includes Intel Turbo Boost) L2MISS: L2 cache misses L2HIT : L2 cache hit ratio (0.00-1.00) TEMP : Temperature reading in 1 degree Celsius relative to the TjMax temperature (thermal headroom): 0 corresponds to the max temperature Core (SKT) | EXEC | IPC | FREQ | L2MISS | L2HIT | TEMP 0 0 0.00 0.20 0.00 5675 0.85 89 1 0 0.00 0.33 0.00 8696 0.80 89 2 0 0.00 0.41 0.01 4598 0.93 N/A 3 0 0.00 0.32 0.00 7239 0.85 N/A ----------------------------------------------------------------------------------------------------------------------------- TOTAL * 0.00 0.33 0.00 26 K 0.86 N/A Instructions retired: 7363 K ; Active cycles: 22 M ; Time (TSC): 1766 Mticks ; C0 (active,non-halted) core residency: 0.31 % C1 core residency: 99.69 %; C2 package residency: 0.00 %; C4 package residency: 0.00 %; C6 package residency: 0.00 %; PHYSICAL CORE IPC : 1.34 => corresponds to 66.84 % utilization for cores in active state Instructions per nominal CPU cycle: 0.00 => corresponds to 0.21 % core utilization over time interval ---------------------------------------------------------------------------------------------- Cleaning up Zeroed PMU registers Freeing up all RMIDs Script done on Sun May 24 00:07:23 2015 Need more or is this enough? -Kimmo