From owner-svn-src-head@FreeBSD.ORG Mon Oct 13 19:14:14 2008 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 825E4106568C; Mon, 13 Oct 2008 19:14:14 +0000 (UTC) (envelope-from raj@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 710408FC19; Mon, 13 Oct 2008 19:14:14 +0000 (UTC) (envelope-from raj@FreeBSD.org) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id m9DJEEiA084116; Mon, 13 Oct 2008 19:14:14 GMT (envelope-from raj@svn.freebsd.org) Received: (from raj@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id m9DJEEJN084115; Mon, 13 Oct 2008 19:14:14 GMT (envelope-from raj@svn.freebsd.org) Message-Id: <200810131914.m9DJEEJN084115@svn.freebsd.org> From: Rafal Jaworowski Date: Mon, 13 Oct 2008 19:14:14 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r183839 - head/sys/arm/arm X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 13 Oct 2008 19:14:14 -0000 Author: raj Date: Mon Oct 13 19:14:14 2008 New Revision: 183839 URL: http://svn.freebsd.org/changeset/base/183839 Log: One more L2 cache synchronization call that didn't make the previous commit. Modified: head/sys/arm/arm/locore.S Modified: head/sys/arm/arm/locore.S ============================================================================== --- head/sys/arm/arm/locore.S Mon Oct 13 18:59:59 2008 (r183838) +++ head/sys/arm/arm/locore.S Mon Oct 13 19:14:14 2008 (r183839) @@ -245,6 +245,8 @@ ENTRY_NP(cpu_halt) ldr r0, .Lcpufuncs mov lr, pc ldr pc, [r0, #CF_IDCACHE_WBINV_ALL] + mov lr, pc + ldr pc, [r0, #CF_L2CACHE_WBINV_ALL] /* * Load the cpu_reset_needs_v4_MMU_disable flag to determine if it's