From owner-cvs-all Fri May 24 14:41: 4 2002 Delivered-To: cvs-all@freebsd.org Received: from mail.viasoft.com.cn (ip-167-164-97-218.anlai.com [218.97.164.167]) by hub.freebsd.org (Postfix) with ESMTP id 4889537B401; Fri, 24 May 2002 14:40:50 -0700 (PDT) Received: from davidwnt (davidwnt.viasoft.com.cn [192.168.1.239]) by mail.viasoft.com.cn (8.9.3/8.9.3) with SMTP id RAA00528; Wed, 22 May 2002 17:48:39 +0800 Message-ID: <000701c20173$0d5498f0$ef01a8c0@davidwnt> From: "David Xu" To: "Doug Rabson" , , References: <200205212021.g4LKLsN48148@freefall.freebsd.org> <200205220947.11913.dfr@nlsystems.com> Subject: Re: cvs commit: src/sys/i386/include cpufunc.h Date: Wed, 22 May 2002 17:28:34 +0800 MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable X-Priority: 3 X-MSMail-Priority: Normal X-Mailer: Microsoft Outlook Express 6.00.2600.0000 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2600.0000 Sender: owner-cvs-all@FreeBSD.ORG Precedence: bulk List-ID: List-Archive: (Web Archive) List-Help: (List Instructions) List-Subscribe: List-Unsubscribe: X-Loop: FreeBSD.ORG Cut from "IA-32 Intel=AE Architecture Software Developer's Manual Volume = 2: Instruction Set Reference", here is the description: PAUSE-Spin Loop Hint Opcode Instruction Description F3 90 PAUSE Gives hint to processor that improves performance of = spin-wait loops. Description Improves the performance of spin-wait loops. When executing a "spin-wait = loop," a Pentium 4 or Intel Xeon processor suffers a severe performance penalty when = exiting the loop because it detects a possible memory order violation. The PAUSE instruction = provides a hint to the processor that the code sequence is a spin-wait loop. The processor uses = this hint to avoid the memory order violation in most situations, which greatly improves = processor performance. For this reason, it is recommended that a PAUSE instruction be placed in all = spin-wait loops. An additional function of the PAUSE instruction is to reduce the power = consumed by a Pentium 4 processor while executing a spin loop. The Pentium 4 processor can = execute a spin-wait loop extremely quickly, causing the processor to consume a lot of power while = it waits for the resource it is spinning on to become available. Inserting a pause = instruction in a spin-wait loop greatly reduces the processor's power consumption. This instruction was introduced in the Pentium 4 processors, but is = backward compatible with all IA-32 processors. In earlier IA-32 processors, the PAUSE instruction = operates like a NOP instruction. The Pentium 4 and Intel Xeon processors implement the PAUSE = instruction as a pre-defined delay. The delay is finite and can be zero for some = processors. This instruction does not change the architectural state of the processor (that is, it = performs essentially a delaying noop operation). Operation Execute_Next_Instruction(DELAY); Protected Mode Exceptions None. Real-Address Mode Exceptions None. Virtual-8086 Mode Exceptions None. Numeric Exceptions None. -- David Xu ----- Original Message -----=20 From: "Doug Rabson" To: "John Baldwin" ; ; = Sent: Wednesday, May 22, 2002 4:47 PM Subject: Re: cvs commit: src/sys/i386/include cpufunc.h On Tuesday 21 May 2002 9:21 pm, John Baldwin wrote: > jhb 2002/05/21 13:21:54 PDT > > Modified files: > sys/i386/include cpufunc.h > Log: > Add an inline function cpu_pause() for the IA32 'pause' instruction. Is this the hyperthreading thing that you are supposed to call from the = idle=20 loop? To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe cvs-all" in the body of the message