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From: Marcel Moolenaar <marcel@FreeBSD.org>
Date: Tue, 16 Sep 2008 17:22:16 +0000 (UTC)
To: src-committers@FreeBSD.org, cvs-src@FreeBSD.org, cvs-all@FreeBSD.org
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Subject: cvs commit: src/sys/powerpc/aim mp_cpudep.c
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marcel      2008-09-16 17:22:16 UTC

  FreeBSD src repository

  Modified files:
    sys/powerpc/aim      mp_cpudep.c 
  Log:
  SVN rev 183090 on 2008-09-16 17:22:16Z by marcel
  
  Rewrite cpudep_ap_bootstrap(). We now enable L3, L2, L1D and L1I
  caches if not yet enabed. This is required for coherency and
  atomic operations to work, not to mention performance. We use the
  L2 and L3 cache settings of the BSP to configure the APs caches.
  Can't be bad.
  
  Program NAP and not DOZE. DOZE is present only on earlier CPUs
  and the bit is reserved on the MPC7441 & MPC7451. NAP will do
  bus snooping to keep caches coherent.
  
  Program the PIR with the cpuid. This may not be necessary...
  
  Revision  Changes    Path
  1.4       +110 -14   src/sys/powerpc/aim/mp_cpudep.c