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Date:      Mon, 25 Jul 2011 18:42:45 +0000 (UTC)
From:      Marius Strobl <marius@FreeBSD.org>
To:        cvs-src-old@freebsd.org
Subject:   cvs commit: src/sys/boot/sparc64/loader main.c src/sys/sparc64/include cache.h cpu.h tlb.h src/sys/sparc64/sparc64 cache.c cheetah.c machdep.c mp_machdep.c pmap.c spitfire.c zeus.c
Message-ID:  <201107251843.p6PIh9nS097196@repoman.freebsd.org>

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marius      2011-07-25 18:42:45 UTC

  FreeBSD src repository

  Modified files:        (Branch: RELENG_7)
    sys/boot/sparc64/loader main.c 
    sys/sparc64/include  cache.h cpu.h tlb.h 
    sys/sparc64/sparc64  cache.c cheetah.c machdep.c mp_machdep.c 
                         pmap.c spitfire.c zeus.c 
  Log:
  SVN rev 224371 on 2011-07-25 18:42:45Z by marius
  
  MFC: r223719
  
  - For Cheetah- and Zeus-class CPUs don't flush all unlocked entries from
    the TLBs in order to get rid of the user mappings but instead traverse
    them an flush only the latter like we also do for the Spitfire-class.
    Also flushing the unlocked kernel entries can cause instant faults which
    when called from within cpu_switch() are handled with the scheduler lock
    held which in turn can cause timeouts on the acquisition of the lock by
    other CPUs. This was easily seen with a 16-core V890 but occasionally
    also happened with 2-way machines.
    While at it, move the SPARC64-V support code entirely to zeus.c. This
    causes a little bit of duplication but is less confusing than partially
    using Cheetah-class bits for these.
  - For SPARC64-V ensure that 4-Mbyte page entries are stored in the 1024-
    entry, 2-way set associative TLB.
  - In {d,i}tlb_get_data_sun4u() turn off the interrupts in order to ensure
    that ASI_{D,I}TLB_DATA_ACCESS_REG actually are read twice back-to-back.
  
  Tested by:      Peter Jeremy (16-core US-IV), Michael Moll (2-way SPARC64-V)
  
  Revision    Changes    Path
  1.32.2.15   +63 -25    src/sys/boot/sparc64/loader/main.c
  1.13.2.6    +5 -4      src/sys/sparc64/include/cache.h
  1.17.2.3    +1 -0      src/sys/sparc64/include/cpu.h
  1.26.22.5   +14 -1     src/sys/sparc64/include/tlb.h
  1.20.10.7   +3 -3      src/sys/sparc64/sparc64/cache.c
  1.5.20.10   +79 -28    src/sys/sparc64/sparc64/cheetah.c
  1.138.2.24  +3 -2      src/sys/sparc64/sparc64/machdep.c
  1.36.2.19   +4 -2      src/sys/sparc64/sparc64/mp_machdep.c
  1.166.2.22  +14 -7     src/sys/sparc64/sparc64/pmap.c
  1.5.20.5    +18 -20    src/sys/sparc64/sparc64/spitfire.c
  1.1.4.3     +107 -1    src/sys/sparc64/sparc64/zeus.c



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