From owner-svn-src-all@FreeBSD.ORG Fri Jan 22 20:32:07 2010 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 86188106566C; Fri, 22 Jan 2010 20:32:07 +0000 (UTC) (envelope-from imp@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 748B28FC0A; Fri, 22 Jan 2010 20:32:07 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id o0MKW71r077745; Fri, 22 Jan 2010 20:32:07 GMT (envelope-from imp@svn.freebsd.org) Received: (from imp@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id o0MKW79x077742; Fri, 22 Jan 2010 20:32:07 GMT (envelope-from imp@svn.freebsd.org) Message-Id: <201001222032.o0MKW79x077742@svn.freebsd.org> From: Warner Losh Date: Fri, 22 Jan 2010 20:32:07 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r202830 - in head/sys/mips: include mips X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Jan 2010 20:32:07 -0000 Author: imp Date: Fri Jan 22 20:32:07 2010 New Revision: 202830 URL: http://svn.freebsd.org/changeset/base/202830 Log: Create a method of last resort for rebooting the mips processor: jump to the reset vector. This works for many SoCs where other reset hardware is either missing or unknown. Modified: head/sys/mips/include/md_var.h head/sys/mips/mips/machdep.c Modified: head/sys/mips/include/md_var.h ============================================================================== --- head/sys/mips/include/md_var.h Fri Jan 22 20:30:54 2010 (r202829) +++ head/sys/mips/include/md_var.h Fri Jan 22 20:32:07 2010 (r202830) @@ -52,6 +52,7 @@ uintptr_t MipsEmulateBranch(struct trapf void MipsSwitchFPState(struct thread *, struct trapframe *); u_long kvtop(void *addr); int is_physical_memory(vm_offset_t addr); +void mips_generic_reset(void); #define is_cacheable_mem(pa) is_physical_memory((pa)) Modified: head/sys/mips/mips/machdep.c ============================================================================== --- head/sys/mips/mips/machdep.c Fri Jan 22 20:30:54 2010 (r202829) +++ head/sys/mips/mips/machdep.c Fri Jan 22 20:32:07 2010 (r202830) @@ -84,6 +84,7 @@ __FBSDID("$FreeBSD$"); #include #include #include +#include #include #include #include @@ -359,6 +360,17 @@ mips_vector_init(void) } /* + * Many SoCs have a means to reset the core itself. Others do not, or + * the method is unknown to us. For those cases, we jump to the mips + * reset vector and hope for the best. This works well in practice. + */ +void +mips_generic_reset() +{ + ((void(*)(void))(intptr_t)MIPS_VEC_RESET)(); +} + +/* * Initialise a struct pcpu. */ void