From owner-svn-src-head@freebsd.org Sat Nov 25 22:03:26 2017 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id D049CDF177A; Sat, 25 Nov 2017 22:03:26 +0000 (UTC) (envelope-from nwhitehorn@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 9A4F870AD7; Sat, 25 Nov 2017 22:03:26 +0000 (UTC) (envelope-from nwhitehorn@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id vAPM3Pxg060048; Sat, 25 Nov 2017 22:03:25 GMT (envelope-from nwhitehorn@FreeBSD.org) Received: (from nwhitehorn@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id vAPM3P31060047; Sat, 25 Nov 2017 22:03:25 GMT (envelope-from nwhitehorn@FreeBSD.org) Message-Id: <201711252203.vAPM3P31060047@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: nwhitehorn set sender to nwhitehorn@FreeBSD.org using -f From: Nathan Whitehorn Date: Sat, 25 Nov 2017 22:03:25 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r326207 - head/sys/powerpc/aim X-SVN-Group: head X-SVN-Commit-Author: nwhitehorn X-SVN-Commit-Paths: head/sys/powerpc/aim X-SVN-Commit-Revision: 326207 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.25 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 25 Nov 2017 22:03:26 -0000 Author: nwhitehorn Date: Sat Nov 25 22:03:25 2017 New Revision: 326207 URL: https://svnweb.freebsd.org/changeset/base/326207 Log: Preserve the LPCR on new-ish (POWER7 and POWER8) CPUs, preventing exceptions and such from ending on the wrong CPU on SMP systems. It would be good to have this be more generic somehow as POWER9s appear, but PPC does not have features bits, unfortunately. MFC after: 3 weeks Modified: head/sys/powerpc/aim/mp_cpudep.c Modified: head/sys/powerpc/aim/mp_cpudep.c ============================================================================== --- head/sys/powerpc/aim/mp_cpudep.c Sat Nov 25 22:01:55 2017 (r326206) +++ head/sys/powerpc/aim/mp_cpudep.c Sat Nov 25 22:03:25 2017 (r326207) @@ -374,6 +374,13 @@ cpudep_ap_setup() reg = mpc74xx_l1i_enable(); break; + case IBMPOWER7: + case IBMPOWER7PLUS: + case IBMPOWER8: + case IBMPOWER8E: + if (mfmsr() & PSL_HV) + mtspr(SPR_LPCR, mfspr(SPR_LPCR) | LPCR_LPES); + break; default: #ifdef __powerpc64__ if (!(mfmsr() & PSL_HV)) /* Rely on HV to have set things up */