From owner-freebsd-amd64@FreeBSD.ORG Wed Dec 1 10:02:03 2004 Return-Path: Delivered-To: freebsd-amd64@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 3403916A4CF for ; Wed, 1 Dec 2004 10:02:03 +0000 (GMT) Received: from wproxy.gmail.com (wproxy.gmail.com [64.233.184.204]) by mx1.FreeBSD.org (Postfix) with ESMTP id B460C43D2D for ; Wed, 1 Dec 2004 10:02:02 +0000 (GMT) (envelope-from astrodog@gmail.com) Received: by wproxy.gmail.com with SMTP id 50so213318wri for ; Wed, 01 Dec 2004 02:02:02 -0800 (PST) DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=beta; d=gmail.com; h=received:message-id:date:from:reply-to:to:subject:cc:in-reply-to:mime-version:content-type:content-transfer-encoding:references; b=LBTPHNIruULb3aB62Vzr+pSFmI6zytOA2Lh2eBRjy4UQ5ST5aASIHTQIOtMzTCmRuybMbVFcnr9R9GMqWzOG8bdc8rBtrTCjFYmHufGvULE+E0RNm5hr/fAHcED7R9RAIM9vOw+TZhZKArtP0gWU6wHutYBwR1PcHd9GrkDTJzQ= Received: by 10.54.30.59 with SMTP id d59mr592436wrd; Wed, 01 Dec 2004 02:02:02 -0800 (PST) Received: by 10.54.40.6 with HTTP; Wed, 1 Dec 2004 02:02:02 -0800 (PST) Message-ID: <2fd864e04120102022a1f5a7a@mail.gmail.com> Date: Wed, 1 Dec 2004 02:02:02 -0800 From: Astrodog To: obrien@freebsd.org In-Reply-To: <20041201090024.GC1621@dragon.nuxi.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit References: <606711.1101483235019.SLOX.WebMail.wwwrun@hermes.aboutit.co.za> <41A80A0F.9030502@gmail.com> <20041201090024.GC1621@dragon.nuxi.com> cc: freebsd-amd64@freebsd.org Subject: Re: Page fault on Tyan K8S Pro (S2882) board X-BeenThere: freebsd-amd64@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list Reply-To: Astrodog List-Id: Porting FreeBSD to the AMD64 platform List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 01 Dec 2004 10:02:03 -0000 Isn't CPU0 blocked from memory, while CPU1 makes a request (and has it fulfilled?) If not... how'd they manage that? Thats cool as hell. Heh. --- Harrison Grundy On Wed, 1 Dec 2004 01:00:24 -0800, David O'Brien wrote: > On Fri, Nov 26, 2004 at 09:01:03PM -0800, Astrodog wrote: > > Running 1 DIMM in this kind of setup is > > shooting yourself in the foot. If CPU #1 requests something through CPU > > #0, and we're using 1 bank of memory the whole setup..... performance is > > gonna be crap. Both CPUs will be blocked from processing instructions > > while the request is fulfilled. > > That is not at all true -- CPU0 is not blocked because CPU1 is accessing > memory directly attached to CPU0. The memory controller in an Opteron > operates independently of the CPU cache unit and central processing unit > ("core"). All of the the HyperTransport connections (3 of them), the > memory controller, cache unit (2 for dual-core) all attach together thru > a cross-bar switch. > > > > There are known performance issues with the 4+0 memory config... but > > they're still good if you use 2 or 4 DIMMs. > > There aren't performance issues with 4+0 memory configurations -- unless > you also consider it a "performance issue" if one is using DDR333 or > DDR266 memory vs. DDR400. CPU1 has a higher latency to memory than CPU0, > 105ns vs. 70ns; BUT 105ns is still lower than the latency of going thru a > traditional northbridge. > > So its all a trade off of where you want to be on the performance curve. > > -- > -- David (obrien@FreeBSD.org) >