From owner-svn-src-all@freebsd.org Thu Nov 7 17:34:45 2019 Return-Path: Delivered-To: svn-src-all@mailman.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.nyi.freebsd.org (Postfix) with ESMTP id 5FC4F1BAC7B; Thu, 7 Nov 2019 17:34:45 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) server-signature RSA-PSS (4096 bits) client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4789Wn1rwDz416q; Thu, 7 Nov 2019 17:34:45 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 23901194DB; Thu, 7 Nov 2019 17:34:45 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id xA7HYj41044247; Thu, 7 Nov 2019 17:34:45 GMT (envelope-from andrew@FreeBSD.org) Received: (from andrew@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id xA7HYjvM044246; Thu, 7 Nov 2019 17:34:45 GMT (envelope-from andrew@FreeBSD.org) Message-Id: <201911071734.xA7HYjvM044246@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: andrew set sender to andrew@FreeBSD.org using -f From: Andrew Turner Date: Thu, 7 Nov 2019 17:34:45 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r354452 - head/sys/arm64/include X-SVN-Group: head X-SVN-Commit-Author: andrew X-SVN-Commit-Paths: head/sys/arm64/include X-SVN-Commit-Revision: 354452 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Nov 2019 17:34:45 -0000 Author: andrew Date: Thu Nov 7 17:34:44 2019 New Revision: 354452 URL: https://svnweb.freebsd.org/changeset/base/354452 Log: Add more 8 and 16 bit variants of the the atomic(9) functions on arm64. These are direct copies of the 32 bit functions, adjusted ad needed. While here fix atomic_fcmpset_16 to use the valid load and store exclusive instructions. Sponsored by: DARPA, AFRL Modified: head/sys/arm64/include/atomic.h Modified: head/sys/arm64/include/atomic.h ============================================================================== --- head/sys/arm64/include/atomic.h Thu Nov 7 17:21:17 2019 (r354451) +++ head/sys/arm64/include/atomic.h Thu Nov 7 17:34:44 2019 (r354452) @@ -57,6 +57,40 @@ #define ATOMIC_OP(op, asm_op, bar, a, l) \ static __inline void \ +atomic_##op##_##bar##8(volatile uint8_t *p, uint8_t val) \ +{ \ + uint8_t tmp; \ + int res; \ + \ + __asm __volatile( \ + "1: ld"#a"xrb %w0, [%2] \n" \ + " "#asm_op" %w0, %w0, %w3 \n" \ + " st"#l"xrb %w1, %w0, [%2] \n" \ + " cbnz %w1, 1b \n" \ + : "=&r"(tmp), "=&r"(res) \ + : "r" (p), "r" (val) \ + : "memory" \ + ); \ +} \ + \ +static __inline void \ +atomic_##op##_##bar##16(volatile uint16_t *p, uint16_t val) \ +{ \ + uint16_t tmp; \ + int res; \ + \ + __asm __volatile( \ + "1: ld"#a"xrh %w0, [%2] \n" \ + " "#asm_op" %w0, %w0, %w3 \n" \ + " st"#l"xrh %w1, %w0, [%2] \n" \ + " cbnz %w1, 1b \n" \ + : "=&r"(tmp), "=&r"(res) \ + : "r" (p), "r" (val) \ + : "memory" \ + ); \ +} \ + \ +static __inline void \ atomic_##op##_##bar##32(volatile uint32_t *p, uint32_t val) \ { \ uint32_t tmp; \ @@ -135,10 +169,10 @@ atomic_fcmpset_##bar##16(volatile uint16_t *p, uint16_ \ __asm __volatile( \ "1: mov %w1, #1 \n" \ - " ld"#a"xh %w0, [%2] \n" \ + " ld"#a"xrh %w0, [%2] \n" \ " cmp %w0, %w3 \n" \ " b.ne 2f \n" \ - " st"#l"xh %w1, %w4, [%2] \n" \ + " st"#l"xrh %w1, %w4, [%2] \n" \ "2:" \ : "=&r"(tmp), "=&r"(res) \ : "r" (p), "r" (_cmpval), "r" (newval) \ @@ -204,6 +238,52 @@ ATOMIC_FCMPSET(rel_, ,l) #undef ATOMIC_FCMPSET #define ATOMIC_CMPSET(bar, a, l) \ +static __inline int \ +atomic_cmpset_##bar##8(volatile uint8_t *p, uint8_t cmpval, \ + uint8_t newval) \ +{ \ + uint8_t tmp; \ + int res; \ + \ + __asm __volatile( \ + "1: mov %w1, #1 \n" \ + " ld"#a"xrb %w0, [%2] \n" \ + " cmp %w0, %w3 \n" \ + " b.ne 2f \n" \ + " st"#l"xrb %w1, %w4, [%2] \n" \ + " cbnz %w1, 1b \n" \ + "2:" \ + : "=&r"(tmp), "=&r"(res) \ + : "r" (p), "r" (cmpval), "r" (newval) \ + : "cc", "memory" \ + ); \ + \ + return (!res); \ +} \ + \ +static __inline int \ +atomic_cmpset_##bar##16(volatile uint16_t *p, uint16_t cmpval, \ + uint16_t newval) \ +{ \ + uint16_t tmp; \ + int res; \ + \ + __asm __volatile( \ + "1: mov %w1, #1 \n" \ + " ld"#a"xrh %w0, [%2] \n" \ + " cmp %w0, %w3 \n" \ + " b.ne 2f \n" \ + " st"#l"xrh %w1, %w4, [%2] \n" \ + " cbnz %w1, 1b \n" \ + "2:" \ + : "=&r"(tmp), "=&r"(res) \ + : "r" (p), "r" (cmpval), "r" (newval) \ + : "cc", "memory" \ + ); \ + \ + return (!res); \ +} \ + \ static __inline int \ atomic_cmpset_##bar##32(volatile uint32_t *p, uint32_t cmpval, \ uint32_t newval) \