Date: Mon, 12 Nov 2007 03:20:57 GMT From: Coleman Kane <cokane@FreeBSD.org> To: freebsd-gnats-submit@FreeBSD.org Subject: ports/117993: misc/cpuid add AMD Miscellanous Features (0x80000001 ECX) Message-ID: <200711120320.lAC3KvNK016140@www.freebsd.org> Resent-Message-ID: <200711120330.lAC3U1S7060341@freefall.freebsd.org>
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>Number: 117993 >Category: ports >Synopsis: misc/cpuid add AMD Miscellanous Features (0x80000001 ECX) >Confidential: no >Severity: non-critical >Priority: medium >Responsible: freebsd-ports-bugs >State: open >Quarter: >Keywords: >Date-Required: >Class: update >Submitter-Id: current-users >Arrival-Date: Mon Nov 12 03:30:01 UTC 2007 >Closed-Date: >Last-Modified: >Originator: Coleman Kane >Release: 8.0-CURRENT >Organization: FreeBSD Project >Environment: FreeBSD erwin 8.0-CURRENT FreeBSD 8.0-CURRENT #0: Sun Nov 11 08:06:05 EST 2007 root@erwin:/usr/obj/usr/src/sys/ERWIN amd64 >Description: The AMD Athlon chip populates ECX with a number of useful feature bits, according to the description of CPUID function 0x80000001. This includes the new AMD-V (SVM bit) support identifier. I have added this and a number of other useful bits to a loop that reads the contents of ECX. >How-To-Repeat: np >Fix: Patch attached with submission follows: diff -r -u misc/cpuid.orig/Makefile misc/cpuid/Makefile --- misc/cpuid.orig/Makefile 2006-11-14 15:49:38.000000000 -0500 +++ misc/cpuid/Makefile 2007-11-11 22:16:22.000000000 -0500 @@ -8,7 +8,7 @@ PORTNAME= cpuid PORTVERSION= 3.3 -PORTREVISION= 3 +PORTREVISION= 4 CATEGORIES= misc MASTER_SITES= http://www.ka9q.net/code/cpuid/ diff -r -u misc/cpuid.orig/files/patch-cpuid.c misc/cpuid/files/patch-cpuid.c --- misc/cpuid.orig/files/patch-cpuid.c 2006-11-14 15:49:38.000000000 -0500 +++ misc/cpuid/files/patch-cpuid.c 2007-11-11 22:16:06.000000000 -0500 @@ -1,5 +1,5 @@ ---- cpuid.c.orig Tue Nov 14 10:17:30 2006 -+++ cpuid.c Tue Nov 14 11:24:57 2006 +--- cpuid.c.orig 2002-01-02 01:14:51.000000000 -0500 ++++ cpuid.c 2007-11-11 22:12:08.000000000 -0500 @@ -10,6 +10,8 @@ * http://developer.intel.com/design/Pentium4/manuals/24547103.pdf * http://developer.intel.com/design/pentiumiii/applnots/24512501.pdf (AP-909) @@ -326,7 +326,7 @@ case 0x82: printf("2nd-level cache: 256KB, 8-way set assoc, 32 byte line size\n"); break; -@@ -486,44 +655,97 @@ +@@ -486,44 +655,132 @@ case 0x85: printf("2nd-level cache: 2MB, 8-way set assoc, 32 byte line size\n"); break; @@ -447,16 +447,51 @@ + "MMX MMX instructions", + "FXSR Fast FP/MMX Streaming SIMD Extensions save/restore", + "FFXSR FXSAVE and FXRSTOR instruction optimizations", -+ "26 Reserved", ++ "Pge1GB 1GB Page Support", + "RDTSCP RDTSCP instruction", + "28 Reserved", + "LM 64 bit long mode", + "3DNowE 3DNow! instruction extensions", + "3DNow 3DNow! instructions", ++}; ++ ++char *AMD_feature_flags3[] = { ++ "LhfSaf LAHF and SAHF instructions in 65-bit mode", ++ "CmpLeg Core Multi-Processing mode", ++ "SVM Secure Virtual Machine", ++ "XAPSPC Extended APIC Register Space", ++ "AltMC8 LOCK MOV CR0 means MOV CR8", ++ "ABM Advanced Bit Manipulation", ++ "SSE4A EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD support", ++ "MASSE Misaligned SSE mode", ++ "3DNPFC PREFETCH and PREFETCHW support", ++ "OSVW OS Visible Workaround support", ++ "10 Reserved", ++ "11 Reserved", ++ "SKINIT SKINIT, STGI, and DEV support", ++ "WDT Watchdog Timer support" ++ "14 Reserved", ++ "15 Reserved", ++ "16 Reserved", ++ "17 Reserved", ++ "18 Reserved", ++ "19 Reserved", ++ "20 Reserved", ++ "21 Reserved", ++ "22 Reserved", ++ "23 Reserved", ++ "24 Reserved", ++ "25 Reserved", ++ "26 Reserved", ++ "27 Reserved", ++ "28 Reserved", ++ "29 Reserved", ++ "30 Reserved", ++ "31 Reserved", }; char *Assoc[] = { -@@ -657,7 +879,7 @@ +@@ -657,10 +914,16 @@ printf("Global Paging Extensions\n"); } else { if(edx & (1<<i)){ @@ -465,3 +500,12 @@ } } } ++ printf("\nExtended Miscellaneous feature flags %08lx:\n", ecx); ++ for(i=0;i<32;i++){ ++ if(ecx & (1<<i)){ ++ printf("%s\n",AMD_feature_flags3[i]); ++ } ++ } + } + printf("\n"); + if(maxei >= 0x80000002){ >Release-Note: >Audit-Trail: >Unformatted:
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