Date: Fri, 07 Jun 2024 00:27:02 +0000 From: bugzilla-noreply@freebsd.org To: bugs@FreeBSD.org Subject: [Bug 271826] FreeBSD is disastrously slow on a PowerMac G5, freezing at every command Message-ID: <bug-271826-227-Pe9PdnaWub@https.bugs.freebsd.org/bugzilla/> In-Reply-To: <bug-271826-227@https.bugs.freebsd.org/bugzilla/> References: <bug-271826-227@https.bugs.freebsd.org/bugzilla/>
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https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=3D271826 --- Comment #36 from Justin Hibbits <jhibbits@FreeBSD.org> --- (In reply to Mitch from comment #35) mpc85xx platforms I've personally tested with FreeBSD are the AmigaOne X5000 and AmigaOne A1222. I wrote the mpc85xx timebase sync specifically for tho= se targets, after seeing strange hanging behavior. As for why we want to use memory barriers, we really need just execution barriers (isync), I think, because we need to make sure the timebase is cor= rect before it's unlocked by the BSP. This can only be ensured by using a barri= er between setting the timebase and declaring done (atomic_add_int() of cpu_do= ne). But, yes, a weak memory model does mean we need more explicit syncs where = on strong models they would be implicit (but pay the penalty on all accesses). We really shouldn't need any syncs for tb_ready, because it can be done laz= ily. The only sync we should really need is the cpu_done. Before this timebase sync we used a synchronization mechanism at AP launch time, where we simply "hoped" that they were close enough to all get the sa= me timebase. This is obviously problematic. It was changed during the 12-CUR= RENT time frame. The powermac sync change was done in 2021, though. --=20 You are receiving this mail because: You are the assignee for the bug.=
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