From owner-svn-src-all@freebsd.org Sat Aug 26 15:08:28 2017 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id D5B75DD41B9; Sat, 26 Aug 2017 15:08:28 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 952CA6E6E4; Sat, 26 Aug 2017 15:08:28 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id v7QF8R4w017661; Sat, 26 Aug 2017 15:08:27 GMT (envelope-from andrew@FreeBSD.org) Received: (from andrew@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id v7QF8RaQ017660; Sat, 26 Aug 2017 15:08:27 GMT (envelope-from andrew@FreeBSD.org) Message-Id: <201708261508.v7QF8RaQ017660@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: andrew set sender to andrew@FreeBSD.org using -f From: Andrew Turner Date: Sat, 26 Aug 2017 15:08:27 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r322924 - head/contrib/cortex-strings/src/aarch64 X-SVN-Group: head X-SVN-Commit-Author: andrew X-SVN-Commit-Paths: head/contrib/cortex-strings/src/aarch64 X-SVN-Commit-Revision: 322924 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 26 Aug 2017 15:08:29 -0000 Author: andrew Date: Sat Aug 26 15:08:27 2017 New Revision: 322924 URL: https://svnweb.freebsd.org/changeset/base/322924 Log: Work around a bug in QEMU when loading data with a load pair instruction where the source register is also the first destination register. If this is the case, and we raise an exception in the middle of the instruction, for example the load is across two pages and the second page isn't mapped, QEMU will have overwritten the address with invalid data. This is a valid behaviour in most cases, with the exception of when a destination register is also use in address generation. As such switch the order of the registers to ensure the address register is second so it will be written to second, after any exceptions have happened. This has been acknowledged in upstream QEMU, however as the workaround is simple also handle it here. Sponsored by: DARPA, AFRL Modified: head/contrib/cortex-strings/src/aarch64/memcpy.S Modified: head/contrib/cortex-strings/src/aarch64/memcpy.S ============================================================================== --- head/contrib/cortex-strings/src/aarch64/memcpy.S Sat Aug 26 14:07:24 2017 (r322923) +++ head/contrib/cortex-strings/src/aarch64/memcpy.S Sat Aug 26 15:08:27 2017 (r322924) @@ -77,8 +77,8 @@ #define D_h x13 #define E_l src #define E_h count -#define F_l srcend -#define F_h dst +#define F_l dst +#define F_h srcend #define tmp1 x9 #define L(l) .L ## l