From owner-svn-src-head@FreeBSD.ORG Sun Jun 15 15:12:11 2014 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id B489961E; Sun, 15 Jun 2014 15:12:11 +0000 (UTC) Received: from gromit.grondar.org (grandfather.grondar.org [IPv6:2a01:348:0:15:5d59:5c20:0:2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 7460222B5; Sun, 15 Jun 2014 15:12:11 +0000 (UTC) Received: from [2001:470:9174:1:29c2:f380:e45f:e04a] by gromit.grondar.org with esmtpsa (TLSv1:AES128-SHA:128) (Exim 4.80.1 (FreeBSD)) (envelope-from ) id 1WwC6D-000HJO-U8; Sun, 15 Jun 2014 16:12:07 +0100 Subject: Re: svn commit: r266083 - in head/sys/arm: arm include Mime-Version: 1.0 (Mac OS X Mail 7.3 \(1878.2\)) Content-Type: text/plain; charset=windows-1252 From: Mark R V Murray In-Reply-To: <9B438991-C970-46A7-8116-A490E02D7139@fh-muenster.de> Date: Sun, 15 Jun 2014 16:13:08 +0100 Content-Transfer-Encoding: quoted-printable Message-Id: <3841D090-5973-40B0-B61C-F15E8C1978C9@FreeBSD.org> References: <201405141911.s4EJBFZZ097826@svn.freebsd.org> <537D0952.2040001@selasky.org> <7610C8E6-3F01-4317-BC1A-67645A162CD7@FreeBSD.org> <53871493.2010502@selasky.org> <9412A358-EBCB-4A5A-B728-2A15C50FC217@fh-muenster.de> <9B438991-C970-46A7-8116-A490E02D7139@fh-muenster.de> To: Michael Tuexen X-Mailer: Apple Mail (2.1878.2) X-SA-Score: -1.0 Cc: Hans Petter Selasky , svn-src-head@freebsd.org, svn-src-all@freebsd.org, src-committers@freebsd.org X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 15 Jun 2014 15:12:11 -0000 On 30 May 2014, at 09:42, Michael Tuexen wrote: > On 29 May 2014, at 21:21, Mark R V Murray wrote: >=20 >>=20 >> On 29 May 2014, at 19:27, Michael Tuexen = wrote: >>=20 >>> On 29 May 2014, at 20:15, Mark R V Murray wrote: >>>=20 >>>>=20 >>>> On 29 May 2014, at 19:13, Michael Tuexen = wrote: >>>>=20 >>>>>> I can make it work on RPI, but trying to find what else it = will/won=92t work on is more problematic. >>>>> Wouldn't it require to use different registers on the RPI? This = would mean you >>>>> would need more #ifdefs=85 >>>>=20 >>>> Thats the problem; too many #ifdefs. >>> So you could just keep the code for now, but reduce the #ifdefs to = the ones you >>> know that work. Later on, you can replace it by the driver stuff=85 >>=20 >> That=92s what I was thinking, yes. > Great. Let me know if you need testing support on the RPI=85 I=92ve come to the conclusion that my RPI-B is hosed. It doesn=92t even = boot Raspian properly. Sorry about how long this has taken. Please could someone with a working RPI please check that the following = patch works (may need to apply by hand due to cut/paste). Thanks, with repeated apologies. M --=20 Mark R V Murray --- include/cpu.h (revision 267507) +++ include/cpu.h (working copy) @@ -25,7 +25,16 @@ * Read PMCCNTR. Curses! Its only 32 bits. * TODO: Fix this by catching overflow with interrupt? */ +/* The ARMv6 vs ARMv7 divide is going to need a better way of + * distinguishing between them. + */ +#if defined(CPU_ARM1136) || defined(CPU_ARM1176) + /* ARMv6 - Earlier model SCCs */ + __asm __volatile("mrc p15, 0, %0, c15, c12, 1": "=3Dr" (ccnt)); +#else + /* ARMv7 - Later model SCCs */ __asm __volatile("mrc p15, 0, %0, c9, c13, 0": "=3Dr" (ccnt)); +#endif ccnt64 =3D (uint64_t)ccnt; return (ccnt64); #else /* No performance counters, so use binuptime(9). This is slooooow = */