From owner-freebsd-hackers@FreeBSD.ORG Tue Apr 26 19:44:43 2005 Return-Path: Delivered-To: freebsd-hackers@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 5B5A116A4CE for ; Tue, 26 Apr 2005 19:44:43 +0000 (GMT) Received: from mail26.sea5.speakeasy.net (mail26.sea5.speakeasy.net [69.17.117.28]) by mx1.FreeBSD.org (Postfix) with ESMTP id 219D543D5E for ; Tue, 26 Apr 2005 19:44:43 +0000 (GMT) (envelope-from jhb@FreeBSD.org) Received: (qmail 4247 invoked from network); 26 Apr 2005 19:44:42 -0000 Received: from server.baldwin.cx ([216.27.160.63]) (envelope-sender )AES256-SHA encrypted SMTP for ; 26 Apr 2005 19:44:42 -0000 Received: from roboboy.corp.weather.com (gw1.twc.weather.com [216.133.140.1]) (authenticated bits=0) by server.baldwin.cx (8.13.1/8.13.1) with ESMTP id j3QJiapS034786; Tue, 26 Apr 2005 15:44:36 -0400 (EDT) (envelope-from jhb@FreeBSD.org) From: John Baldwin To: freebsd-hackers@FreeBSD.org Date: Tue, 26 Apr 2005 14:56:51 -0400 User-Agent: KMail/1.8 References: In-Reply-To: MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200504261456.52070.jhb@FreeBSD.org> X-Spam-Status: No, score=-102.8 required=4.2 tests=ALL_TRUSTED, USER_IN_WHITELIST autolearn=failed version=3.0.2 X-Spam-Checker-Version: SpamAssassin 3.0.2 (2004-11-16) on server.baldwin.cx cc: John Giacomoni Subject: Re: what goes wrong with barrier free atomic_load/store? X-BeenThere: freebsd-hackers@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: Technical Discussions relating to FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 26 Apr 2005 19:44:43 -0000 On Wednesday 20 April 2005 04:39 pm, John Giacomoni wrote: > in reading /src/sys/i386/include/atomic.h > > I found this comment and I'm having trouble understanding what the > problem being > referred to below is. > > /* > * We assume that a = b will do atomic loads and stores. However, on a > * PentiumPro or higher, reads may pass writes, so for that case we have > * to use a serializing instruction (i.e. with LOCK) to do the load in > * SMP kernels. For UP kernels, however, the cache of the single > processor > * is always consistent, so we don't need any memory barriers. > */ > > can someone give me an example of a situation where one needs to use > memory barriers to ensure "correctness" when doing writes as above? > > the examples I can come up with seem to boil down to requiring locks > or accepting stale values, given that without a synchronization > mechanism > one shouldn't expect two processes to act in any specific order. > > In my case I can accept reading a stale value so I'm not understanding > the > purpose of only having atomic_load/atomic_store wrappers with memory > barriers. > > I saw a brief discussion where someone proposed barrier free load/store > but > don't think I saw any resolution. > > thanks, > > John G We use atomic_store_rel() as part of implementing mutexes. -- John Baldwin <>< http://www.FreeBSD.org/~jhb/ "Power Users Use the Power to Serve" = http://www.FreeBSD.org