From owner-svn-src-all@freebsd.org Thu Feb 28 00:30:35 2019 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id C7C0C150A7EC; Thu, 28 Feb 2019 00:30:35 +0000 (UTC) (envelope-from mav@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) server-signature RSA-PSS (4096 bits) client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 69A1F685F0; Thu, 28 Feb 2019 00:30:35 +0000 (UTC) (envelope-from mav@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 5D28D2481C; Thu, 28 Feb 2019 00:30:35 +0000 (UTC) (envelope-from mav@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id x1S0UZbg034923; Thu, 28 Feb 2019 00:30:35 GMT (envelope-from mav@FreeBSD.org) Received: (from mav@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id x1S0UZTh034922; Thu, 28 Feb 2019 00:30:35 GMT (envelope-from mav@FreeBSD.org) Message-Id: <201902280030.x1S0UZTh034922@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: mav set sender to mav@FreeBSD.org using -f From: Alexander Motin Date: Thu, 28 Feb 2019 00:30:35 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-11@freebsd.org Subject: svn commit: r344652 - stable/11/sys/dev/ntb/ntb_hw X-SVN-Group: stable-11 X-SVN-Commit-Author: mav X-SVN-Commit-Paths: stable/11/sys/dev/ntb/ntb_hw X-SVN-Commit-Revision: 344652 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Rspamd-Queue-Id: 69A1F685F0 X-Spamd-Bar: -- Authentication-Results: mx1.freebsd.org X-Spamd-Result: default: False [-2.97 / 15.00]; local_wl_from(0.00)[FreeBSD.org]; NEURAL_HAM_MEDIUM(-1.00)[-0.999,0]; NEURAL_HAM_SHORT(-0.97)[-0.967,0]; NEURAL_HAM_LONG(-1.00)[-0.999,0]; ASN(0.00)[asn:11403, ipnet:2610:1c1:1::/48, country:US] X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Feb 2019 00:30:36 -0000 Author: mav Date: Thu Feb 28 00:30:34 2019 New Revision: 344652 URL: https://svnweb.freebsd.org/changeset/base/344652 Log: MFC r344437: Allow I/OAT of present Xeon E5/E7 to work thorugh PLX NTB. Its a hack, we can't know/list all DMA engines, but this covers all I/OAT of Xeon E5/E7 at least from Sandy Bridge till Skylake I saw. Modified: stable/11/sys/dev/ntb/ntb_hw/ntb_hw_plx.c Directory Properties: stable/11/ (props changed) Modified: stable/11/sys/dev/ntb/ntb_hw/ntb_hw_plx.c ============================================================================== --- stable/11/sys/dev/ntb/ntb_hw/ntb_hw_plx.c Thu Feb 28 00:30:13 2019 (r344651) +++ stable/11/sys/dev/ntb/ntb_hw/ntb_hw_plx.c Thu Feb 28 00:30:34 2019 (r344652) @@ -202,16 +202,24 @@ ntb_plx_init(device_t dev) if (sc->alut) PNTX_WRITE(sc, 0xc94, 0); - /* Enable Link Interface LUT entries 0/1 for peer 0/1. */ - PNTX_WRITE(sc, 0xdb4, 0x00090001); + /* Enable all Link Interface LUT entries for peer. */ + for (i = 0; i < 32; i += 2) { + PNTX_WRITE(sc, 0xdb4 + i * 2, + 0x00010001 | ((i + 1) << 19) | (i << 3)); + } } /* - * Enable Virtual Interface LUT entry 0 for 0:0.0 and - * entry 1 for our Requester ID reported by chip. + * Enable Virtual Interface LUT entry 0 for 0:0.*. + * entry 1 for our Requester ID reported by the chip, + * entries 2-5 for 0/64/128/192:4.* of I/OAT DMA engines. + * XXX: Its a hack, we can't know all DMA engines, but this covers all + * I/OAT of Xeon E5/E7 at least from Sandy Bridge till Skylake I saw. */ val = (NTX_READ(sc, 0xc90) << 16) | 0x00010001; NTX_WRITE(sc, sc->link ? 0xdb4 : 0xd94, val); + NTX_WRITE(sc, sc->link ? 0xdb8 : 0xd98, 0x40210021); + NTX_WRITE(sc, sc->link ? 0xdbc : 0xd9c, 0xc0218021); /* Set Link to Virtual address translation. */ for (i = 0; i < sc->mw_count; i++) {