From owner-svn-src-head@FreeBSD.ORG Mon Jun 16 07:28:57 2014 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 2B0CE698; Mon, 16 Jun 2014 07:28:57 +0000 (UTC) Received: from mail-n.franken.de (drew.ipv6.franken.de [IPv6:2001:638:a02:a001:20e:cff:fe4a:feaa]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "mail-n.franken.de", Issuer "Thawte DV SSL CA" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id A94EE2039; Mon, 16 Jun 2014 07:28:56 +0000 (UTC) Received: from [10.225.7.42] (unknown [194.95.73.101]) (Authenticated sender: macmic) by mail-n.franken.de (Postfix) with ESMTP id 388B81C104E82; Mon, 16 Jun 2014 09:28:54 +0200 (CEST) Content-Type: text/plain; charset=windows-1252 Mime-Version: 1.0 (Mac OS X Mail 7.3 \(1878.2\)) Subject: Re: svn commit: r266083 - in head/sys/arm: arm include From: Michael Tuexen In-Reply-To: <3841D090-5973-40B0-B61C-F15E8C1978C9@FreeBSD.org> Date: Mon, 16 Jun 2014 09:28:53 +0200 Content-Transfer-Encoding: quoted-printable Message-Id: <3664DBD3-7CEA-43E8-9757-E835BB21FE9E@freebsd.org> References: <201405141911.s4EJBFZZ097826@svn.freebsd.org> <537D0952.2040001@selasky.org> <7610C8E6-3F01-4317-BC1A-67645A162CD7@FreeBSD.org> <53871493.2010502@selasky.org> <9412A358-EBCB-4A5A-B728-2A15C50FC217@fh-muenster.de> <9B438991-C970-46A7-8116-A490E02D7139@fh-muenster.de> <3841D090-5973-40B0-B61C-F15E8C1978C9@FreeBSD.org> To: Mark R V Murray X-Mailer: Apple Mail (2.1878.2) Cc: Hans Petter Selasky , svn-src-head@freebsd.org, svn-src-all@freebsd.org, src-committers@freebsd.org X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Jun 2014 07:28:57 -0000 On 15 Jun 2014, at 17:13, Mark R V Murray wrote: >=20 > On 30 May 2014, at 09:42, Michael Tuexen = wrote: >=20 >> On 29 May 2014, at 21:21, Mark R V Murray wrote: >>=20 >>>=20 >>> On 29 May 2014, at 19:27, Michael Tuexen = wrote: >>>=20 >>>> On 29 May 2014, at 20:15, Mark R V Murray = wrote: >>>>=20 >>>>>=20 >>>>> On 29 May 2014, at 19:13, Michael Tuexen = wrote: >>>>>=20 >>>>>>> I can make it work on RPI, but trying to find what else it = will/won=92t work on is more problematic. >>>>>> Wouldn't it require to use different registers on the RPI? This = would mean you >>>>>> would need more #ifdefs=85 >>>>>=20 >>>>> Thats the problem; too many #ifdefs. >>>> So you could just keep the code for now, but reduce the #ifdefs to = the ones you >>>> know that work. Later on, you can replace it by the driver stuff=85 >>>=20 >>> That=92s what I was thinking, yes. >> Great. Let me know if you need testing support on the RPI=85 >=20 > I=92ve come to the conclusion that my RPI-B is hosed. It doesn=92t = even boot Raspian properly. Sorry about how long this has taken. >=20 > Please could someone with a working RPI please check that the = following patch works (may need to apply by hand due to cut/paste). Hi Mark, your patch for accessing the value is correct. However, the = initialisation code also needs to be adopted to the platform. So in addition to your patch, you = also need: Index: arm/cpufunc.c =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- arm/cpufunc.c (revision 267519) +++ arm/cpufunc.c (working copy) @@ -1415,6 +1415,12 @@ : : "r"(0x00000001)); #endif +#if defined(CPU_ARM1136) || defined(CPU_ARM1176) + /* Set PMCR[2,0] to enable counters and reset CCNT */ + __asm volatile ("mcr p15, 0, %0, c15, c12, 0\n\t" + : + : "r"(0x00000005)); +#else /* Set up the PMCCNTR register as a cyclecounter: * Set PMINTENCLR to 0xFFFFFFFF to block interrupts * Set PMCR[2,0] to enable counters and reset CCNT @@ -1426,6 +1432,7 @@ : "r"(0xFFFFFFFF), "r"(0x00000005), "r"(0x80000000)); +#endif } #endif =20 With both patches, the RPI boots up fine with r267519 Is there an easy test to see if the code actually works as expected and = not that it just allows the system to boot? Regarding the 32-bit limitation: Do we want to increment the register = only every 64 clock cycle? Best regards Michael >=20 > Thanks, with repeated apologies. >=20 > M > --=20 > Mark R V Murray >=20 > --- include/cpu.h (revision 267507) > +++ include/cpu.h (working copy) > @@ -25,7 +25,16 @@ > * Read PMCCNTR. Curses! Its only 32 bits. > * TODO: Fix this by catching overflow with interrupt? > */ > +/* The ARMv6 vs ARMv7 divide is going to need a better way of > + * distinguishing between them. > + */ > +#if defined(CPU_ARM1136) || defined(CPU_ARM1176) > + /* ARMv6 - Earlier model SCCs */ > + __asm __volatile("mrc p15, 0, %0, c15, c12, 1": "=3Dr" (ccnt)); > +#else > + /* ARMv7 - Later model SCCs */ > __asm __volatile("mrc p15, 0, %0, c9, c13, 0": "=3Dr" (ccnt)); > +#endif > ccnt64 =3D (uint64_t)ccnt; > return (ccnt64); > #else /* No performance counters, so use binuptime(9). This is = slooooow */ >=20 >=20