From owner-freebsd-arch@FreeBSD.ORG Wed Dec 19 14:44:23 2012 Return-Path: Delivered-To: freebsd-arch@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id CBA86ACB for ; Wed, 19 Dec 2012 14:44:23 +0000 (UTC) (envelope-from mjacob@freebsd.org) Received: from ns1.feral.com (ns1.feral.com [192.67.166.1]) by mx1.freebsd.org (Postfix) with ESMTP id A07408FC0C for ; Wed, 19 Dec 2012 14:44:23 +0000 (UTC) Received: from [192.168.135.2] (quaver.net [76.14.49.207]) (authenticated bits=0) by ns1.feral.com (8.14.5/8.14.4) with ESMTP id qBJEiGFi076972 (version=TLSv1/SSLv3 cipher=DHE-RSA-CAMELLIA256-SHA bits=256 verify=NO) for ; Wed, 19 Dec 2012 06:44:16 -0800 (PST) (envelope-from mjacob@freebsd.org) Message-ID: <50D1D2BD.80107@freebsd.org> Date: Wed, 19 Dec 2012 06:44:13 -0800 From: Matthew Jacob Organization: FreeBSD User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 To: freebsd-arch@freebsd.org Subject: Re: Unmapped I/O References: <20121219135451.GU71906@kib.kiev.ua> In-Reply-To: <20121219135451.GU71906@kib.kiev.ua> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.2.7 (ns1.feral.com [192.67.166.1]); Wed, 19 Dec 2012 06:44:16 -0800 (PST) X-BeenThere: freebsd-arch@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list Reply-To: mjacob@freebsd.org List-Id: Discussion related to FreeBSD architecture List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 19 Dec 2012 14:44:23 -0000 On 12/19/2012 5:54 AM, Konstantin Belousov wrote: > One of the known FreeBSD I/O path performance bootleneck is the > neccessity to map each I/O buffer pages into KVA. The problem is that > on the multi-core machines, the mapping must flush TLB on all cores, > due to the global mapping of the buffer pages into the kernel. This > means that buffer creation and destruction disrupts execution of all > other cores to perform TLB shootdown through IPI, and the thread > initiating the shootdown must wait for all other cores to execute and > report. > About time!