From owner-svn-src-all@FreeBSD.ORG Sat Oct 26 16:49:41 2013 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTP id C940EE8C; Sat, 26 Oct 2013 16:49:41 +0000 (UTC) (envelope-from nwhitehorn@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.freebsd.org (Postfix) with ESMTPS id 9B7042754; Sat, 26 Oct 2013 16:49:41 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.7/8.14.7) with ESMTP id r9QGnfeQ045168; Sat, 26 Oct 2013 16:49:41 GMT (envelope-from nwhitehorn@svn.freebsd.org) Received: (from nwhitehorn@localhost) by svn.freebsd.org (8.14.7/8.14.5/Submit) id r9QGnfSB045167; Sat, 26 Oct 2013 16:49:41 GMT (envelope-from nwhitehorn@svn.freebsd.org) Message-Id: <201310261649.r9QGnfSB045167@svn.freebsd.org> From: Nathan Whitehorn Date: Sat, 26 Oct 2013 16:49:41 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r257169 - head/sys/powerpc/booke X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 26 Oct 2013 16:49:41 -0000 Author: nwhitehorn Date: Sat Oct 26 16:49:41 2013 New Revision: 257169 URL: http://svnweb.freebsd.org/changeset/base/257169 Log: Fix concurrency issues with TLB1 updates and make pmap_kextract() search TLB1 mappings as well, which is required for the console to work after r257111. Modified: head/sys/powerpc/booke/pmap.c Modified: head/sys/powerpc/booke/pmap.c ============================================================================== --- head/sys/powerpc/booke/pmap.c Sat Oct 26 16:19:14 2013 (r257168) +++ head/sys/powerpc/booke/pmap.c Sat Oct 26 16:49:41 2013 (r257169) @@ -1355,6 +1355,15 @@ mmu_booke_extract(mmu_t mmu, pmap_t pmap static vm_paddr_t mmu_booke_kextract(mmu_t mmu, vm_offset_t va) { + int i; + + /* Check TLB1 mappings */ + for (i = 0; i < tlb1_idx; i++) { + if (!(tlb1[i].mas1 & MAS1_VALID)) + continue; + if (va >= tlb1[i].virt && va < tlb1[i].virt + tlb1[i].size) + return (tlb1[i].phys + (va - tlb1[i].virt)); + } return (pte_vatopa(mmu, kernel_pmap, va)); } @@ -2697,6 +2706,7 @@ mmu_booke_mapdev_attr(mmu_t mmu, vm_padd static void mmu_booke_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) { +#ifdef SUPPORTS_SHRINKING_TLB1 vm_offset_t base, offset; /* @@ -2708,6 +2718,7 @@ mmu_booke_unmapdev(mmu_t mmu, vm_offset_ size = roundup(offset + size, PAGE_SIZE); kva_free(base, size); } +#endif } /* @@ -2974,9 +2985,10 @@ tlb1_set_entry(vm_offset_t va, vm_offset uint32_t flags) { uint32_t ts, tid; - int tsize; - - if (tlb1_idx >= TLB1_ENTRIES) { + int tsize, index; + + index = atomic_fetchadd_int(&tlb1_idx, 1); + if (index >= TLB1_ENTRIES) { printf("tlb1_set_entry: TLB1 full!\n"); return (-1); } @@ -2988,18 +3000,22 @@ tlb1_set_entry(vm_offset_t va, vm_offset /* XXX TS is hard coded to 0 for now as we only use single address space */ ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK; - /* XXX LOCK tlb1[] */ + /* + * Atomicity is preserved by the atomic increment above since nothing + * is ever removed from tlb1. + */ - tlb1[tlb1_idx].mas1 = MAS1_VALID | MAS1_IPROT | ts | tid; - tlb1[tlb1_idx].mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK); - tlb1[tlb1_idx].mas2 = (va & MAS2_EPN_MASK) | flags; + tlb1[index].phys = pa; + tlb1[index].virt = va; + tlb1[index].size = size; + tlb1[index].mas1 = MAS1_VALID | MAS1_IPROT | ts | tid; + tlb1[index].mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK); + tlb1[index].mas2 = (va & MAS2_EPN_MASK) | flags; /* Set supervisor RWX permission bits */ - tlb1[tlb1_idx].mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX; - - tlb1_write_entry(tlb1_idx++); + tlb1[index].mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX; - /* XXX UNLOCK tlb1[] */ + tlb1_write_entry(index); /* * XXX in general TLB1 updates should be propagated between CPUs,