From owner-svn-src-projects@FreeBSD.ORG Sat Sep 13 15:50:59 2014 Return-Path: Delivered-To: svn-src-projects@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 1A035F95; Sat, 13 Sep 2014 15:50:59 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 05BC67E5; Sat, 13 Sep 2014 15:50:59 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.9/8.14.9) with ESMTP id s8DFowV8090486; Sat, 13 Sep 2014 15:50:58 GMT (envelope-from ian@FreeBSD.org) Received: (from ian@localhost) by svn.freebsd.org (8.14.9/8.14.9/Submit) id s8DFowHI090485; Sat, 13 Sep 2014 15:50:58 GMT (envelope-from ian@FreeBSD.org) Message-Id: <201409131550.s8DFowHI090485@svn.freebsd.org> X-Authentication-Warning: svn.freebsd.org: ian set sender to ian@FreeBSD.org using -f From: Ian Lepore Date: Sat, 13 Sep 2014 15:50:58 +0000 (UTC) To: src-committers@freebsd.org, svn-src-projects@freebsd.org Subject: svn commit: r271521 - projects/arm_intrng/sys/arm/arm X-SVN-Group: projects MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-projects@freebsd.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: "SVN commit messages for the src " projects" tree" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 13 Sep 2014 15:50:59 -0000 Author: ian Date: Sat Sep 13 15:50:58 2014 New Revision: 271521 URL: http://svnweb.freebsd.org/changeset/base/271521 Log: Minor changes to work with intrng, mostly involved with using values in the softc struct instead of global/static values. Modified: projects/arm_intrng/sys/arm/arm/gic.c Modified: projects/arm_intrng/sys/arm/arm/gic.c ============================================================================== --- projects/arm_intrng/sys/arm/arm/gic.c Sat Sep 13 15:49:51 2014 (r271520) +++ projects/arm_intrng/sys/arm/arm/gic.c Sat Sep 13 15:50:58 2014 (r271521) @@ -111,7 +111,7 @@ struct arm_gic_softc { static struct resource_spec arm_gic_spec[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE }, /* Distributor registers */ { SYS_RES_MEMORY, 1, RF_ACTIVE }, /* CPU Interrupt Intf. registers */ - { SYS_RES_IRQ, 0, RF_ACTIVE }, /* Parent interrupt */ + { SYS_RES_IRQ, 0, RF_ACTIVE | RF_OPTIONAL }, /* Parent interrupt */ { -1, 0 } }; @@ -140,6 +140,7 @@ static void arm_gic_ipi_clear(device_t, static int arm_gic_probe(device_t dev) { + if (!ofw_bus_status_okay(dev)) return (ENXIO); @@ -153,34 +154,43 @@ static void arm_gic_init_secondary(device_t dev) { struct arm_gic_softc *sc = device_get_softc(dev); - - for (int i = 0; i < sc->nirqs; i += 4) + int i; + + for (i = 0; i < sc->nirqs; i += 4) gic_d_write_4(sc, GICD_IPRIORITYR(i >> 2), 0); /* Set all the interrupts to be in Group 0 (secure) */ - for (i = 0; i < nirqs; i += 32) { - gic_d_write_4(GICD_IGROUPR(i >> 5), 0); + for (i = 0; i < sc->nirqs; i += 32) { + gic_d_write_4(sc, GICD_IGROUPR(i >> 5), 0); } /* Enable CPU interface */ gic_c_write_4(sc, GICC_CTLR, 1); + /* Set priority mask register. */ + gic_c_write_4(sc, GICC_PMR, 0xff); + /* Enable interrupt distribution */ gic_d_write_4(sc, GICD_CTLR, 0x01); /* Activate IRQ 29, ie private timer IRQ*/ /* Activate IRQ 29-30, ie private timer (secure & non-secure) IRQs */ - gic_d_write_4(GICD_ISENABLER(29 >> 5), (1UL << (29 & 0x1F))); - gic_d_write_4(GICD_ISENABLER(30 >> 5), (1UL << (30 & 0x1F))); + gic_d_write_4(sc, GICD_ISENABLER(29 >> 5), (1UL << (29 & 0x1F))); + gic_d_write_4(sc, GICD_ISENABLER(30 >> 5), (1UL << (30 & 0x1F))); } static int arm_gic_attach(device_t dev) { - struct arm_gic_softc *sc = device_get_softc(dev); + struct arm_gic_softc *sc; int i; uint32_t icciidr; + if (arm_gic_sc) + return (ENXIO); + + sc = device_get_softc(dev); + if (bus_alloc_resources(dev, arm_gic_spec, sc->gic_res)) { device_printf(dev, "could not allocate resources\n"); return (ENXIO); @@ -232,8 +242,8 @@ arm_gic_attach(device_t dev) } for (i = 0; i < sc->nirqs; i += 4) { - gic_d_write_4(GICD_IPRIORITYR(i >> 2), 0); - gic_d_write_4(GICD_ITARGETSR(i >> 2), 1 << 0 | 1 << 8 | 1 << 16 | 1 << 24); + gic_d_write_4(sc, GICD_IPRIORITYR(i >> 2), 0); + gic_d_write_4(sc, GICD_ITARGETSR(i >> 2), 1 << 0 | 1 << 8 | 1 << 16 | 1 << 24); } /* Set all the interrupts to be in Group 0 (secure) */ @@ -267,13 +277,13 @@ arm_gic_intr(void *arg) * have this information later. */ - if ((active_irq & 0x3ff) < 1) + if ((active_irq & 0x3ff) <= GIC_LAST_IPI) gic_c_write_4(sc, GICC_EOIR, active_irq); active_irq &= 0x3FF; if (active_irq == 0x3FF) { if (last_irq == -1) - printf("Spurious interrupt detected [0x%08x]\n", active_irq); + printf("Spurious interrupt detected\n"); return (FILTER_HANDLED); } @@ -354,7 +364,7 @@ arm_gic_mask(device_t dev, int irq) struct arm_gic_softc *sc = device_get_softc(dev); gic_d_write_4(sc, GICD_ICENABLER(irq >> 5), (1UL << (irq & 0x1F))); - gic_c_write_4(GICC_EOIR, nb); + gic_c_write_4(sc, GICC_EOIR, irq); } static void @@ -362,8 +372,8 @@ arm_gic_unmask(device_t dev, int irq) { struct arm_gic_softc *sc = device_get_softc(dev); - if (nb > GIC_LAST_IPI) - arm_irq_memory_barrier(nb); + if (irq > GIC_LAST_IPI) + arm_irq_memory_barrier(irq); gic_d_write_4(sc, GICD_ISENABLER(irq >> 5), (1UL << (irq & 0x1F))); } @@ -429,5 +439,8 @@ static driver_t arm_gic_driver = { static devclass_t arm_gic_devclass; -DRIVER_MODULE(gic, simplebus, arm_gic_driver, arm_gic_devclass, 0, 0); +EARLY_DRIVER_MODULE(gic, simplebus, arm_gic_driver, arm_gic_devclass, 0, 0, + BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE); +EARLY_DRIVER_MODULE(gic, ofwbus, arm_gic_driver, arm_gic_devclass, 0, 0, + BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);