Date: Sat, 12 Nov 2011 16:47:24 +0000 (UTC) From: Adrian Chadd <adrian@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r227468 - head/sys/dev/ath/ath_hal/ar5416 Message-ID: <201111121647.pACGlOY7053106@svn.freebsd.org>
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Author: adrian Date: Sat Nov 12 16:47:23 2011 New Revision: 227468 URL: http://svn.freebsd.org/changeset/base/227468 Log: Disable writing to the extension CYCPWR1 register. This seems to make ANI behave better on the AR5416/AR5418. Sponsored by: Hobnob, Inc. Modified: head/sys/dev/ath/ath_hal/ar5416/ar5416_ani.c head/sys/dev/ath/ath_hal/ar5416/ar5416phy.h Modified: head/sys/dev/ath/ath_hal/ar5416/ar5416_ani.c ============================================================================== --- head/sys/dev/ath/ath_hal/ar5416/ar5416_ani.c Sat Nov 12 14:39:20 2011 (r227467) +++ head/sys/dev/ath/ath_hal/ar5416/ar5416_ani.c Sat Nov 12 16:47:23 2011 (r227468) @@ -342,11 +342,6 @@ ar5416AniControl(struct ath_hal *ah, HAL OS_REG_RMW_FIELD(ah, AR_PHY_TIMING5, AR_PHY_TIMING5_CYCPWR_THR1, params->cycPwrThr1[level]); - /* Only set the ext channel cycpwr_thr1 field for ht/40 */ - if (IEEE80211_IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) - OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, - AR_PHY_EXT_TIMING5_CYCPWR_THR1, params->cycPwrThr1[level]); - if (level > aniState->spurImmunityLevel) ahp->ah_stats.ast_ani_spurup++; else if (level < aniState->spurImmunityLevel) Modified: head/sys/dev/ath/ath_hal/ar5416/ar5416phy.h ============================================================================== --- head/sys/dev/ath/ath_hal/ar5416/ar5416phy.h Sat Nov 12 14:39:20 2011 (r227467) +++ head/sys/dev/ath/ath_hal/ar5416/ar5416phy.h Sat Nov 12 16:47:23 2011 (r227468) @@ -121,12 +121,6 @@ #define AR_PHY_EXT_MINCCA_PWR_S 23 #define AR_PHY_EXT_CCA_THRESH62 0x007F0000 #define AR_PHY_EXT_CCA_THRESH62_S 16 -/* - * This duplicates AR_PHY_EXT_CCA_CYCPWR_THR1; it reads more like - * an ANI register this way. - */ -#define AR_PHY_EXT_TIMING5_CYCPWR_THR1 0x0000FE00 -#define AR_PHY_EXT_TIMING5_CYCPWR_THR1_S 9 #define AR9280_PHY_EXT_MINCCA_PWR 0x01FF0000 #define AR9280_PHY_EXT_MINCCA_PWR_S 16
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