Date: Sat, 27 May 2017 04:03:12 -0700 From: Mark Millard <markmi@dsl-only.net> To: Justin Hibbits <jhibbits@FreeBSD.org>, FreeBSD PowerPC ML <freebsd-ppc@freebsd.org>, freebsd-hackers@freebsd.org Subject: Re: A good backtrace from a head -r317820 powerpc random/periodic panic: execution of garbage at 0x0090a030 (in .hash section) [patch now fixed] Message-ID: <DE88CBF5-BE88-4140-93E5-EC0FD9A523A9@dsl-only.net> In-Reply-To: <9D70C580-C545-4EA0-AB76-FE757C1AF60A@dsl-only.net> References: <1CE8346B-04F3-48AB-A3E9-6DF3B86B8D1A@dsl-only.net> <8C88BB6F-E747-42A1-9DDC-35EC6D865141@dsl-only.net> <62BF8E69-E7E6-4C4F-AB33-38B03E903CDA@dsl-only.net> <CF7FA043-23DC-4012-B7D4-3A0E21BE924A@dsl-only.net> <67C79408-0DDC-4A22-BFEC-6EC5DD80F076@dsl-only.net> <9D70C580-C545-4EA0-AB76-FE757C1AF60A@dsl-only.net>
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While the patch probably is still appropriate,
testing has shown that it is not sufficient
to prevent the periodic/random panics that I
have been getting.
=3D=3D=3D
Mark Millard
markmi at dsl-only.net
On 2017-May-27, at 2:12 AM, Mark Millard <markmi@dsl-only.net> wrote:
> [Testing shows the prior patch makes the PowerMac
> G5 so-called "Quad Core" hang very early.]
>=20
> I forgot to deal with the prepare side of things.
> So, now with both prepare and restore code fixes,
> this code boots.
>=20
> # svnlite diff /usr/src/sys/powerpc/ofw/ofw_machdep.c =
=
Index: =
/usr/src/sys/powerpc/ofw/ofw_machdep.c
> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
> --- /usr/src/sys/powerpc/ofw/ofw_machdep.c (revision 317820)
> +++ /usr/src/sys/powerpc/ofw/ofw_machdep.c (working copy)
> @@ -111,26 +111,27 @@
> * Assume that interrupt are disabled at this point, or
> * SPRG1-3 could be trashed
> */
> -#ifdef __powerpc64__
> - __asm __volatile("mtsprg1 %0\n\t"
> - "mtsprg2 %1\n\t"
> - "mtsprg3 %2\n\t"
> - :
> - : "r"(ofmsr[2]),
> - "r"(ofmsr[3]),
> - "r"(ofmsr[4]));
> -#else
> - __asm __volatile("mfsprg0 %0\n\t"
> - "mtsprg0 %1\n\t"
> - "mtsprg1 %2\n\t"
> - "mtsprg2 %3\n\t"
> - "mtsprg3 %4\n\t"
> - : "=3D&r"(ofw_sprg0_save)
> - : "r"(ofmsr[1]),
> - "r"(ofmsr[2]),
> - "r"(ofmsr[3]),
> - "r"(ofmsr[4]));
> +#ifndef __powerpc64__
> + if (!(cpu_features & PPC_FEATURE_64))
> + __asm __volatile("mfsprg0 %0\n\t"
> + "mtsprg0 %1\n\t"
> + "mtsprg1 %2\n\t"
> + "mtsprg2 %3\n\t"
> + "mtsprg3 %4\n\t"
> + : "=3D&r"(ofw_sprg0_save)
> + : "r"(ofmsr[1]),
> + "r"(ofmsr[2]),
> + "r"(ofmsr[3]),
> + "r"(ofmsr[4]));
> + else
> #endif
> + __asm __volatile("mtsprg1 %0\n\t"
> + "mtsprg2 %1\n\t"
> + "mtsprg3 %2\n\t"
> + :
> + : "r"(ofmsr[2]),
> + "r"(ofmsr[3]),
> + "r"(ofmsr[4]));
> }
>=20
> static __inline void
> @@ -147,7 +148,8 @@
> * PCPU data cannot be used until this routine is called !
> */
> #ifndef __powerpc64__
> - __asm __volatile("mtsprg0 %0" :: "r"(ofw_sprg0_save));
> + if (!(cpu_features & PPC_FEATURE_64))
> + __asm __volatile("mtsprg0 %0" :: "r"(ofw_sprg0_save));
> #endif
> }
> #endif
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