From owner-svn-src-stable@FreeBSD.ORG Sun Oct 26 03:52:47 2014 Return-Path: Delivered-To: svn-src-stable@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 838C6121; Sun, 26 Oct 2014 03:52:47 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 6D28628C; Sun, 26 Oct 2014 03:52:47 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.9/8.14.9) with ESMTP id s9Q3qkUJ034012; Sun, 26 Oct 2014 03:52:46 GMT (envelope-from ian@FreeBSD.org) Received: (from ian@localhost) by svn.freebsd.org (8.14.9/8.14.9/Submit) id s9Q3qknf034008; Sun, 26 Oct 2014 03:52:46 GMT (envelope-from ian@FreeBSD.org) Message-Id: <201410260352.s9Q3qknf034008@svn.freebsd.org> X-Authentication-Warning: svn.freebsd.org: ian set sender to ian@FreeBSD.org using -f From: Ian Lepore Date: Sun, 26 Oct 2014 03:52:46 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-10@freebsd.org Subject: svn commit: r273672 - in stable/10/sys/arm: arm freescale/imx include X-SVN-Group: stable-10 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-stable@freebsd.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: SVN commit messages for all the -stable branches of the src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 26 Oct 2014 03:52:47 -0000 Author: ian Date: Sun Oct 26 03:52:45 2014 New Revision: 273672 URL: https://svnweb.freebsd.org/changeset/base/273672 Log: MFC r271595, r271601, r271607, r271630: Add compat strings for all the flavors of GIC this driver should support. Also allow the driver to attach to ofwbus as well as simplebus, some FDT data puts the root interrupt controller on the root bus. Add a common routine for parsing FDT data describing an ARM GIC interrupt. Use gic_decode_fdt() rather than a local routine to parse fdt interrupt properties. Move fdt_pic_table and fdt_fixup_table into imx6_machdep.c, which means imx6 doesn't need imx_common.c anymore. The private peripheral interrupts start at offset 16, not 0. Also, use names rather than inline mystery constants for these offsets. Modified: stable/10/sys/arm/arm/gic.c stable/10/sys/arm/freescale/imx/files.imx6 stable/10/sys/arm/freescale/imx/imx6_machdep.c stable/10/sys/arm/include/intr.h Directory Properties: stable/10/ (props changed) Modified: stable/10/sys/arm/arm/gic.c ============================================================================== --- stable/10/sys/arm/arm/gic.c Sun Oct 26 03:48:12 2014 (r273671) +++ stable/10/sys/arm/arm/gic.c Sun Oct 26 03:52:45 2014 (r273672) @@ -83,7 +83,11 @@ __FBSDID("$FreeBSD$"); #define GICC_ABPR 0x001C /* v1 ICCABPR */ #define GICC_IIDR 0x00FC /* v1 ICCIIDR*/ -#define GIC_LAST_IPI 15 /* Irqs 0-15 are IPIs. */ +#define GIC_FIRST_IPI 0 /* Irqs 0-15 are SGIs/IPIs. */ +#define GIC_LAST_IPI 15 +#define GIC_FIRST_PPI 16 /* Irqs 16-31 are private (per */ +#define GIC_LAST_PPI 31 /* core) peripheral interrupts. */ +#define GIC_FIRST_SPI 32 /* Irqs 32+ are shared peripherals. */ /* First bit is a polarity bit (0 - low, 1 - high) */ #define GICD_ICFGR_POL_LOW (0 << 0) @@ -127,6 +131,17 @@ static int gic_config_irq(int irq, enum enum intr_polarity pol); static void gic_post_filter(void *); +static struct ofw_compat_data compat_data[] = { + {"arm,gic", true}, /* Non-standard, used in FreeBSD dts. */ + {"arm,gic-400", true}, + {"arm,cortex-a15-gic", true}, + {"arm,cortex-a9-gic", true}, + {"arm,cortex-a7-gic", true}, + {"arm,arm11mp-gic", true}, + {"brcm,brahma-b15-gic", true}, + {NULL, false} +}; + static int arm_gic_probe(device_t dev) { @@ -134,7 +149,7 @@ arm_gic_probe(device_t dev) if (!ofw_bus_status_okay(dev)) return (ENXIO); - if (!ofw_bus_is_compatible(dev, "arm,gic")) + if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) return (ENXIO); device_set_desc(dev, "ARM Generic Interrupt Controller"); return (BUS_PROBE_DEFAULT); @@ -170,6 +185,51 @@ gic_init_secondary(void) gic_d_write_4(GICD_ISENABLER(29 >> 5), (1UL << (29 & 0x1F))); } +int +gic_decode_fdt(uint32_t iparent, uint32_t *intr, int *interrupt, + int *trig, int *pol) +{ + static u_int num_intr_cells; + + if (num_intr_cells == 0) { + if (OF_searchencprop(OF_node_from_xref(iparent), + "#interrupt-cells", &num_intr_cells, + sizeof(num_intr_cells)) == -1) { + num_intr_cells = 1; + } + } + + if (num_intr_cells == 1) { + *interrupt = fdt32_to_cpu(intr[0]); + *trig = INTR_TRIGGER_CONFORM; + *pol = INTR_POLARITY_CONFORM; + } else { + if (intr[0] == 0) + *interrupt = fdt32_to_cpu(intr[1]) + GIC_FIRST_SPI; + else + *interrupt = fdt32_to_cpu(intr[1]) + GIC_FIRST_PPI; + /* + * In intr[2], bits[3:0] are trigger type and level flags. + * 1 = low-to-high edge triggered + * 2 = high-to-low edge triggered + * 4 = active high level-sensitive + * 8 = active low level-sensitive + * The hardware only supports active-high-level or rising-edge. + */ + if (intr[2] & 0x0a) { + printf("unsupported trigger/polarity configuration " + "0x%2x\n", intr[2] & 0x0f); + return (ENOTSUP); + } + *pol = INTR_POLARITY_CONFORM; + if (intr[2] & 0x01) + *trig = INTR_TRIGGER_EDGE; + else + *trig = INTR_TRIGGER_LEVEL; + } + return (0); +} + static int arm_gic_attach(device_t dev) { @@ -265,6 +325,8 @@ static devclass_t arm_gic_devclass; EARLY_DRIVER_MODULE(gic, simplebus, arm_gic_driver, arm_gic_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE); +EARLY_DRIVER_MODULE(gic, ofwbus, arm_gic_driver, arm_gic_devclass, 0, 0, + BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE); static void gic_post_filter(void *arg) Modified: stable/10/sys/arm/freescale/imx/files.imx6 ============================================================================== --- stable/10/sys/arm/freescale/imx/files.imx6 Sun Oct 26 03:48:12 2014 (r273671) +++ stable/10/sys/arm/freescale/imx/files.imx6 Sun Oct 26 03:52:45 2014 (r273672) @@ -23,7 +23,6 @@ arm/freescale/imx/imx6_ccm.c standard arm/freescale/imx/imx6_machdep.c standard arm/freescale/imx/imx6_mp.c optional smp arm/freescale/imx/imx6_pl310.c standard -arm/freescale/imx/imx_common.c standard arm/freescale/imx/imx_iomux.c standard arm/freescale/imx/imx_machdep.c standard arm/freescale/imx/imx_gpt.c standard Modified: stable/10/sys/arm/freescale/imx/imx6_machdep.c ============================================================================== --- stable/10/sys/arm/freescale/imx/imx6_machdep.c Sun Oct 26 03:48:12 2014 (r273671) +++ stable/10/sys/arm/freescale/imx/imx6_machdep.c Sun Oct 26 03:52:45 2014 (r273672) @@ -38,6 +38,7 @@ __FBSDID("$FreeBSD$"); #include #include +#include #include #include @@ -45,6 +46,18 @@ __FBSDID("$FreeBSD$"); #include #include +#include +#include + +struct fdt_fixup_entry fdt_fixup_table[] = { + { NULL, NULL } +}; + +fdt_pic_decode_t fdt_pic_table[] = { + &gic_decode_fdt, + NULL +}; + vm_offset_t initarm_lastaddr(void) { Modified: stable/10/sys/arm/include/intr.h ============================================================================== --- stable/10/sys/arm/include/intr.h Sun Oct 26 03:48:12 2014 (r273671) +++ stable/10/sys/arm/include/intr.h Sun Oct 26 03:52:45 2014 (r273672) @@ -82,5 +82,7 @@ extern int (*arm_config_irq)(int irq, en void arm_irq_memory_barrier(uintptr_t); void gic_init_secondary(void); +int gic_decode_fdt(uint32_t iparentnode, uint32_t *intrcells, int *interrupt, + int *trig, int *pol); #endif /* _MACHINE_INTR_H */