From owner-freebsd-arch@FreeBSD.ORG Sun May 22 04:21:48 2005 Return-Path: X-Original-To: freebsd-arch@freebsd.org Delivered-To: freebsd-arch@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 9BDB216A41F; Sun, 22 May 2005 04:21:48 +0000 (GMT) (envelope-from marcel@xcllnt.net) Received: from ns1.xcllnt.net (209-128-86-226.bayarea.net [209.128.86.226]) by mx1.FreeBSD.org (Postfix) with ESMTP id 2659943D1F; Sun, 22 May 2005 04:21:48 +0000 (GMT) (envelope-from marcel@xcllnt.net) Received: from [192.168.4.250] (dhcp50.pn.xcllnt.net [192.168.4.250]) by ns1.xcllnt.net (8.13.3/8.13.3) with ESMTP id j4M4LlJb023710; Sat, 21 May 2005 21:21:48 -0700 (PDT) (envelope-from marcel@xcllnt.net) In-Reply-To: <428FE788.8020408@freebsd.org> References: <428FC00B.3080909@freebsd.org> <428FD710.4060200@freebsd.org> <9e8314b53980a379445cc8c07086901d@xcllnt.net> <428FE788.8020408@freebsd.org> Mime-Version: 1.0 (Apple Message framework v622) Content-Type: text/plain; charset=US-ASCII; format=flowed Message-Id: <6451b639f2e0ddacb18f62c571dfeedb@xcllnt.net> Content-Transfer-Encoding: 7bit From: Marcel Moolenaar Date: Sat, 21 May 2005 21:21:47 -0700 To: Colin Percival X-Mailer: Apple Mail (2.622) cc: freebsd-arch@freebsd.org Subject: Re: Scheduler fixes for hyperthreading X-BeenThere: freebsd-arch@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: Discussion related to FreeBSD architecture List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 22 May 2005 04:21:48 -0000 On May 21, 2005, at 6:59 PM, Colin Percival wrote: > Marcel Moolenaar wrote: >> On May 21, 2005, at 5:49 PM, Colin Percival wrote: >>> Put simply, threads which share a processor core can monitor each >>> others' >>> memory access patterns, so we need to ensure that such co-scheduling >>> never >>> happens between threads which have different privileges. >> >> I'll be studying your paper to see if it can be shown that the HT >> implementation in Itanium is affected as well. > > My understanding is that there are no currently released ia64 > processors > with hyperthreading support, but that some future ia64 processor(s) are > likely to be affected. There are a lot of variables that need to be taken into account and those variables do not necessarily map perfectly from a P4 to an I2. Sharing of the L1 cache is not a sufficient condition to create a side-channel for timing attacks. A reliable time source with enough precision is also necessary (as you and Stephan have pointed out). The precision of the time source depends on latencies of the various cache levels and the micro-architectural behavior of the processor. All I'm saying is: remain precise and careful. -- Marcel Moolenaar USPA: A-39004 marcel@xcllnt.net