Date: Sat, 11 May 2002 14:20:05 -0700 (PDT) From: Jake Burkholder <jake@FreeBSD.org> To: cvs-committers@FreeBSD.org, cvs-all@FreeBSD.org Subject: cvs commit: src/lib/libc/sparc64/fpu fpu.c fpu_explode.c src/lib/libc/sparc64/sys __sparc_utrap_emul.c src/sys/sparc64/include instr.h Message-ID: <200205112120.g4BLK5q45292@freefall.freebsd.org>
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jake 2002/05/11 14:20:05 PDT
Modified files:
lib/libc/sparc64/fpu fpu.c fpu_explode.c
lib/libc/sparc64/sys __sparc_utrap_emul.c
sys/sparc64/include instr.h
Log:
Add a support macro to convert the 5-bit packed register field of
a floating point instruction into a 6-bit register number for
double and quad arguments.
Make use of the new INSFPdq_RN macro where apporpriate; this
is required for correctly handling the "high" fp registers
(>= %f32).
Fix a number of bugs related to the handling of the high registers
which were caused by using __fpu_[gs]etreg() where __fpu_[gs]etreg64()
should be used (the former can only access the low, single-precision,
registers).
Submitted by: tmm
Revision Changes Path
1.6 +74 -52 src/lib/libc/sparc64/fpu/fpu.c
1.5 +14 -10 src/lib/libc/sparc64/fpu/fpu_explode.c
1.2 +2 -4 src/lib/libc/sparc64/sys/__sparc_utrap_emul.c
1.4 +3 -0 src/sys/sparc64/include/instr.h
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