From owner-svn-src-all@FreeBSD.ORG Fri Nov 12 15:20:11 2010 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 42A99106566B; Fri, 12 Nov 2010 15:20:11 +0000 (UTC) (envelope-from nwhitehorn@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 2F3E78FC1B; Fri, 12 Nov 2010 15:20:11 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id oACFKB6M012877; Fri, 12 Nov 2010 15:20:11 GMT (envelope-from nwhitehorn@svn.freebsd.org) Received: (from nwhitehorn@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id oACFKAlp012872; Fri, 12 Nov 2010 15:20:10 GMT (envelope-from nwhitehorn@svn.freebsd.org) Message-Id: <201011121520.oACFKAlp012872@svn.freebsd.org> From: Nathan Whitehorn Date: Fri, 12 Nov 2010 15:20:10 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r215182 - in head/sys/powerpc: aim include powerpc X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 12 Nov 2010 15:20:11 -0000 Author: nwhitehorn Date: Fri Nov 12 15:20:10 2010 New Revision: 215182 URL: http://svn.freebsd.org/changeset/base/215182 Log: Add CPU support code for the IBM Cell Broadband Engine. Modified: head/sys/powerpc/aim/mp_cpudep.c head/sys/powerpc/include/cpufunc.h head/sys/powerpc/include/spr.h head/sys/powerpc/powerpc/cpu.c Modified: head/sys/powerpc/aim/mp_cpudep.c ============================================================================== --- head/sys/powerpc/aim/mp_cpudep.c Fri Nov 12 14:40:20 2010 (r215181) +++ head/sys/powerpc/aim/mp_cpudep.c Fri Nov 12 15:20:10 2010 (r215182) @@ -228,6 +228,21 @@ cpudep_save_config(void *dummy) powerpc_sync(); break; +#ifdef __powerpc64__ + case IBMCELLBE: + if (mfmsr() & PSL_HV) { + bsp_state[0] = mfspr(SPR_HID0); + bsp_state[1] = mfspr(SPR_HID1); + bsp_state[2] = mfspr(SPR_HID4); + bsp_state[3] = mfspr(SPR_HID6); + + bsp_state[4] = mfspr(SPR_CELL_TSCR); + } + + bsp_state[5] = mfspr(SPR_CELL_TSRL); + + break; +#endif case MPC7450: case MPC7455: case MPC7457: @@ -288,6 +303,21 @@ cpudep_ap_setup() powerpc_sync(); break; +#ifdef __powerpc64__ + case IBMCELLBE: + if (mfmsr() & PSL_HV) { + mtspr(SPR_HID0, bsp_state[0]); + mtspr(SPR_HID1, bsp_state[1]); + mtspr(SPR_HID4, bsp_state[2]); + mtspr(SPR_HID6, bsp_state[3]); + + mtspr(SPR_CELL_TSCR, bsp_state[4]); + } + + mtspr(SPR_CELL_TSRL, bsp_state[5]); + + break; +#endif case MPC7450: case MPC7455: case MPC7457: Modified: head/sys/powerpc/include/cpufunc.h ============================================================================== --- head/sys/powerpc/include/cpufunc.h Fri Nov 12 14:40:20 2010 (r215181) +++ head/sys/powerpc/include/cpufunc.h Fri Nov 12 15:20:10 2010 (r215182) @@ -106,6 +106,17 @@ mfsrin(vm_offset_t va) } #endif +static __inline register_t +mfctrl(void) +{ + register_t value; + + __asm __volatile ("mfspr %0,136" : "=r"(value)); + + return (value); +} + + static __inline void mtdec(register_t value) { Modified: head/sys/powerpc/include/spr.h ============================================================================== --- head/sys/powerpc/include/spr.h Fri Nov 12 14:40:20 2010 (r215181) +++ head/sys/powerpc/include/spr.h Fri Nov 12 15:20:10 2010 (r215182) @@ -420,6 +420,10 @@ #define SPR_HID1 0x3f1 /* ..8 Hardware Implementation Register 1 */ #define SPR_HID4 0x3f4 /* ..8 Hardware Implementation Register 4 */ #define SPR_HID5 0x3f6 /* ..8 Hardware Implementation Register 5 */ +#define SPR_HID6 0x3f9 /* ..8 Hardware Implementation Register 6 */ + +#define SPR_CELL_TSRL 0x380 /* ... Cell BE Thread Status Register */ +#define SPR_CELL_TSCR 0x399 /* ... Cell BE Thread Switch Register */ #if defined(AIM) #define SPR_DBSR 0x3f0 /* 4.. Debug Status Register */ Modified: head/sys/powerpc/powerpc/cpu.c ============================================================================== --- head/sys/powerpc/powerpc/cpu.c Fri Nov 12 14:40:20 2010 (r215181) +++ head/sys/powerpc/powerpc/cpu.c Fri Nov 12 15:20:10 2010 (r215182) @@ -149,6 +149,9 @@ static const struct cputab models[] = { 0, cpu_e500_setup }, { "Freescale e500v2 core", FSL_E500v2, REVFMT_MAJMIN, 0, cpu_e500_setup }, + { "IBM Cell Broadband Engine", IBMCELLBE, REVFMT_MAJMIN, + PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, + NULL}, { "Unknown PowerPC CPU", 0, REVFMT_HEX, 0, NULL }, };