From owner-svn-src-stable@FreeBSD.ORG Wed Oct 24 19:04:18 2012 Return-Path: Delivered-To: svn-src-stable@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 2C995E7; Wed, 24 Oct 2012 19:04:18 +0000 (UTC) (envelope-from gavin@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 0EFFD8FC0C; Wed, 24 Oct 2012 19:04:18 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.4/8.14.4) with ESMTP id q9OJ4ITT076878; Wed, 24 Oct 2012 19:04:18 GMT (envelope-from gavin@svn.freebsd.org) Received: (from gavin@localhost) by svn.freebsd.org (8.14.4/8.14.4/Submit) id q9OJ4Hbr076861; Wed, 24 Oct 2012 19:04:17 GMT (envelope-from gavin@svn.freebsd.org) Message-Id: <201210241904.q9OJ4Hbr076861@svn.freebsd.org> From: Gavin Atkinson Date: Wed, 24 Oct 2012 19:04:17 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-9@freebsd.org Subject: svn commit: r242015 - in stable/9/sys: dev/alc dev/bge dev/cxgb dev/cxgbe dev/e1000 dev/et dev/jme dev/pci dev/re ofed/include/linux powerpc/mpc85xx X-SVN-Group: stable-9 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-stable@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: SVN commit messages for all the -stable branches of the src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 24 Oct 2012 19:04:18 -0000 Author: gavin Date: Wed Oct 24 19:04:17 2012 New Revision: 242015 URL: http://svn.freebsd.org/changeset/base/242015 Log: Merge r240680 from head: Align the PCI Express #defines with the style used for the PCI-X #defines. This has the advantage that it makes the names more compact, and also allows us to correct the non-uniform naming of the PCIM_LINK_* defines, making them all consistent amongst themselves. This is a mostly mechanical rename: s/PCIR_EXPRESS_/PCIER_/g s/PCIM_EXP_/PCIEM_/g s/PCIM_LINK_/PCIEM_LINK_/g In this MFC, #defines have been added for the old names to assist out-of-tree drivers. Modified: stable/9/sys/dev/alc/if_alc.c stable/9/sys/dev/bge/if_bge.c stable/9/sys/dev/cxgb/cxgb_main.c stable/9/sys/dev/cxgb/cxgb_osdep.h stable/9/sys/dev/cxgbe/osdep.h stable/9/sys/dev/cxgbe/t4_main.c stable/9/sys/dev/e1000/if_em.c stable/9/sys/dev/et/if_et.c stable/9/sys/dev/jme/if_jme.c stable/9/sys/dev/pci/pci.c stable/9/sys/dev/pci/pcireg.h stable/9/sys/dev/re/if_re.c stable/9/sys/ofed/include/linux/pci.h stable/9/sys/powerpc/mpc85xx/pci_fdt.c Directory Properties: stable/9/sys/ (props changed) stable/9/sys/dev/ (props changed) stable/9/sys/dev/e1000/ (props changed) Modified: stable/9/sys/dev/alc/if_alc.c ============================================================================== --- stable/9/sys/dev/alc/if_alc.c Wed Oct 24 18:36:41 2012 (r242014) +++ stable/9/sys/dev/alc/if_alc.c Wed Oct 24 19:04:17 2012 (r242015) @@ -683,7 +683,7 @@ alc_aspm(struct alc_softc *sc, int media if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == (ALC_FLAG_APS | ALC_FLAG_PCIE)) linkcfg = CSR_READ_2(sc, sc->alc_expcap + - PCIR_EXPRESS_LINK_CTL); + PCIER_LINK_CTL); else linkcfg = 0; pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; @@ -698,7 +698,7 @@ alc_aspm(struct alc_softc *sc, int media if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && sc->alc_rev == ATHEROS_AR8152_B_V10) linkcfg |= 0x80; - CSR_WRITE_2(sc, sc->alc_expcap + PCIR_EXPRESS_LINK_CTL, + CSR_WRITE_2(sc, sc->alc_expcap + PCIER_LINK_CTL, linkcfg); pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | PM_CFG_HOTRST); @@ -798,10 +798,10 @@ alc_attach(device_t dev) if (pci_find_cap(dev, PCIY_EXPRESS, &base) == 0) { sc->alc_flags |= ALC_FLAG_PCIE; sc->alc_expcap = base; - burst = CSR_READ_2(sc, base + PCIR_EXPRESS_DEVICE_CTL); + burst = CSR_READ_2(sc, base + PCIER_DEVICE_CTL); sc->alc_dma_rd_burst = - (burst & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12; - sc->alc_dma_wr_burst = (burst & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5; + (burst & PCIEM_CTL_MAX_READ_REQUEST) >> 12; + sc->alc_dma_wr_burst = (burst & PCIEM_CTL_MAX_PAYLOAD) >> 5; if (bootverbose) { device_printf(dev, "Read request size : %u bytes.\n", alc_dma_burst[sc->alc_dma_rd_burst]); @@ -831,9 +831,9 @@ alc_attach(device_t dev) CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); } /* Disable ASPM L0S and L1. */ - cap = CSR_READ_2(sc, base + PCIR_EXPRESS_LINK_CAP); - if ((cap & PCIM_LINK_CAP_ASPM) != 0) { - ctl = CSR_READ_2(sc, base + PCIR_EXPRESS_LINK_CTL); + cap = CSR_READ_2(sc, base + PCIER_LINK_CAP); + if ((cap & PCIEM_LINK_CAP_ASPM) != 0) { + ctl = CSR_READ_2(sc, base + PCIER_LINK_CTL); if ((ctl & 0x08) != 0) sc->alc_rcb = DMA_CFG_RCB_128; if (bootverbose) Modified: stable/9/sys/dev/bge/if_bge.c ============================================================================== --- stable/9/sys/dev/bge/if_bge.c Wed Oct 24 18:36:41 2012 (r242014) +++ stable/9/sys/dev/bge/if_bge.c Wed Oct 24 19:04:17 2012 (r242015) @@ -3650,17 +3650,17 @@ bge_reset(struct bge_softc *sc) pci_write_config(dev, 0xC4, val | (1 << 15), 4); } devctl = pci_read_config(dev, - sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, 2); + sc->bge_expcap + PCIER_DEVICE_CTL, 2); /* Clear enable no snoop and disable relaxed ordering. */ - devctl &= ~(PCIM_EXP_CTL_RELAXED_ORD_ENABLE | - PCIM_EXP_CTL_NOSNOOP_ENABLE); - pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, + devctl &= ~(PCIEM_CTL_RELAXED_ORD_ENABLE | + PCIEM_CTL_NOSNOOP_ENABLE); + pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_CTL, devctl, 2); /* Clear error status. */ - pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_STA, - PCIM_EXP_STA_CORRECTABLE_ERROR | - PCIM_EXP_STA_NON_FATAL_ERROR | PCIM_EXP_STA_FATAL_ERROR | - PCIM_EXP_STA_UNSUPPORTED_REQ, 2); + pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_STA, + PCIEM_STA_CORRECTABLE_ERROR | + PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR | + PCIEM_STA_UNSUPPORTED_REQ, 2); } /* Reset some of the PCI state that got zapped by reset. */ Modified: stable/9/sys/dev/cxgb/cxgb_main.c ============================================================================== --- stable/9/sys/dev/cxgb/cxgb_main.c Wed Oct 24 18:36:41 2012 (r242014) +++ stable/9/sys/dev/cxgb/cxgb_main.c Wed Oct 24 19:04:17 2012 (r242015) @@ -476,8 +476,8 @@ cxgb_controller_attach(device_t dev) if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { uint16_t lnk; - lnk = pci_read_config(dev, reg + PCIR_EXPRESS_LINK_STA, 2); - sc->link_width = (lnk & PCIM_LINK_STA_WIDTH) >> 4; + lnk = pci_read_config(dev, reg + PCIER_LINK_STA, 2); + sc->link_width = (lnk & PCIEM_LINK_STA_WIDTH) >> 4; if (sc->link_width < 8 && (ai->caps & SUPPORTED_10000baseT_Full)) { device_printf(sc->dev, Modified: stable/9/sys/dev/cxgb/cxgb_osdep.h ============================================================================== --- stable/9/sys/dev/cxgb/cxgb_osdep.h Wed Oct 24 18:36:41 2012 (r242014) +++ stable/9/sys/dev/cxgb/cxgb_osdep.h Wed Oct 24 19:04:17 2012 (r242015) @@ -215,11 +215,11 @@ static const int debug_flags = DBG_RX; #define PCI_VPD_DATA PCIR_VPD_DATA #define PCI_CAP_ID_EXP PCIY_EXPRESS -#define PCI_EXP_DEVCTL PCIR_EXPRESS_DEVICE_CTL -#define PCI_EXP_DEVCTL_PAYLOAD PCIM_EXP_CTL_MAX_PAYLOAD -#define PCI_EXP_DEVCTL_READRQ PCIM_EXP_CTL_MAX_READ_REQUEST -#define PCI_EXP_LNKCTL PCIR_EXPRESS_LINK_CTL -#define PCI_EXP_LNKSTA PCIR_EXPRESS_LINK_STA +#define PCI_EXP_DEVCTL PCIER_DEVICE_CTL +#define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD +#define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST +#define PCI_EXP_LNKCTL PCIER_LINK_CTL +#define PCI_EXP_LNKSTA PCIER_LINK_STA /* * Linux compatibility macros Modified: stable/9/sys/dev/cxgbe/osdep.h ============================================================================== --- stable/9/sys/dev/cxgbe/osdep.h Wed Oct 24 18:36:41 2012 (r242014) +++ stable/9/sys/dev/cxgbe/osdep.h Wed Oct 24 19:04:17 2012 (r242015) @@ -118,13 +118,13 @@ typedef boolean_t bool; #define PCI_VPD_DATA PCIR_VPD_DATA #define PCI_CAP_ID_EXP PCIY_EXPRESS -#define PCI_EXP_DEVCTL PCIR_EXPRESS_DEVICE_CTL -#define PCI_EXP_DEVCTL_PAYLOAD PCIM_EXP_CTL_MAX_PAYLOAD -#define PCI_EXP_DEVCTL_READRQ PCIM_EXP_CTL_MAX_READ_REQUEST -#define PCI_EXP_LNKCTL PCIR_EXPRESS_LINK_CTL -#define PCI_EXP_LNKSTA PCIR_EXPRESS_LINK_STA -#define PCI_EXP_LNKSTA_CLS PCIM_LINK_STA_SPEED -#define PCI_EXP_LNKSTA_NLW PCIM_LINK_STA_WIDTH +#define PCI_EXP_DEVCTL PCIER_DEVICE_CTL +#define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD +#define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST +#define PCI_EXP_LNKCTL PCIER_LINK_CTL +#define PCI_EXP_LNKSTA PCIER_LINK_STA +#define PCI_EXP_LNKSTA_CLS PCIEM_LINK_STA_SPEED +#define PCI_EXP_LNKSTA_NLW PCIEM_LINK_STA_WIDTH #define PCI_EXP_DEVCTL2 0x28 static inline int Modified: stable/9/sys/dev/cxgbe/t4_main.c ============================================================================== --- stable/9/sys/dev/cxgbe/t4_main.c Wed Oct 24 18:36:41 2012 (r242014) +++ stable/9/sys/dev/cxgbe/t4_main.c Wed Oct 24 19:04:17 2012 (r242015) @@ -430,9 +430,9 @@ t4_attach(device_t dev) uint32_t v; pci_set_max_read_req(dev, 4096); - v = pci_read_config(dev, i + PCIR_EXPRESS_DEVICE_CTL, 2); - v |= PCIM_EXP_CTL_RELAXED_ORD_ENABLE; - pci_write_config(dev, i + PCIR_EXPRESS_DEVICE_CTL, v, 2); + v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2); + v |= PCIEM_CTL_RELAXED_ORD_ENABLE; + pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2); } snprintf(sc->lockname, sizeof(sc->lockname), "%s", Modified: stable/9/sys/dev/e1000/if_em.c ============================================================================== --- stable/9/sys/dev/e1000/if_em.c Wed Oct 24 18:36:41 2012 (r242014) +++ stable/9/sys/dev/e1000/if_em.c Wed Oct 24 19:04:17 2012 (r242015) @@ -5111,11 +5111,11 @@ em_disable_aspm(struct adapter *adapter) } if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0) return; - reg = base + PCIR_EXPRESS_LINK_CAP; + reg = base + PCIER_LINK_CAP; link_cap = pci_read_config(dev, reg, 2); - if ((link_cap & PCIM_LINK_CAP_ASPM) == 0) + if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0) return; - reg = base + PCIR_EXPRESS_LINK_CTL; + reg = base + PCIER_LINK_CTL; link_ctrl = pci_read_config(dev, reg, 2); link_ctrl &= 0xFFFC; /* turn off bit 1 and 2 */ pci_write_config(dev, reg, link_ctrl, 2); Modified: stable/9/sys/dev/et/if_et.c ============================================================================== --- stable/9/sys/dev/et/if_et.c Wed Oct 24 18:36:41 2012 (r242014) +++ stable/9/sys/dev/et/if_et.c Wed Oct 24 19:04:17 2012 (r242015) @@ -700,8 +700,8 @@ et_bus_config(struct et_softc *sc) * max playload size */ val = pci_read_config(sc->dev, - sc->sc_expcap + PCIR_EXPRESS_DEVICE_CAP, 4); - max_plsz = val & PCIM_EXP_CAP_MAX_PAYLOAD; + sc->sc_expcap + PCIER_DEVICE_CAP, 4); + max_plsz = val & PCIEM_CAP_MAX_PAYLOAD; switch (max_plsz) { case ET_PCIV_DEVICE_CAPS_PLSZ_128: @@ -732,7 +732,7 @@ et_bus_config(struct et_softc *sc) * Set L0s and L1 latency timer to 2us */ val = pci_read_config(sc->dev, ET_PCIR_L0S_L1_LATENCY, 4); - val &= ~(PCIM_LINK_CAP_L0S_EXIT | PCIM_LINK_CAP_L1_EXIT); + val &= ~(PCIEM_LINK_CAP_L0S_EXIT | PCIEM_LINK_CAP_L1_EXIT); /* L0s exit latency : 2us */ val |= 0x00005000; /* L1 exit latency : 2us */ Modified: stable/9/sys/dev/jme/if_jme.c ============================================================================== --- stable/9/sys/dev/jme/if_jme.c Wed Oct 24 18:36:41 2012 (r242014) +++ stable/9/sys/dev/jme/if_jme.c Wed Oct 24 19:04:17 2012 (r242015) @@ -778,7 +778,7 @@ jme_attach(device_t dev) /* Set max allowable DMA size. */ if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { sc->jme_flags |= JME_FLAG_PCIE; - burst = pci_read_config(dev, i + PCIR_EXPRESS_DEVICE_CTL, 2); + burst = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2); if (bootverbose) { device_printf(dev, "Read request size : %d bytes.\n", 128 << ((burst >> 12) & 0x07)); Modified: stable/9/sys/dev/pci/pci.c ============================================================================== --- stable/9/sys/dev/pci/pci.c Wed Oct 24 18:36:41 2012 (r242014) +++ stable/9/sys/dev/pci/pci.c Wed Oct 24 19:04:17 2012 (r242015) @@ -1722,8 +1722,8 @@ pci_get_max_read_req(device_t dev) if (pci_find_cap(dev, PCIY_EXPRESS, &cap) != 0) return (0); - val = pci_read_config(dev, cap + PCIR_EXPRESS_DEVICE_CTL, 2); - val &= PCIM_EXP_CTL_MAX_READ_REQUEST; + val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); + val &= PCIEM_CTL_MAX_READ_REQUEST; val >>= 12; return (1 << (val + 7)); } @@ -1741,10 +1741,10 @@ pci_set_max_read_req(device_t dev, int s if (size > 4096) size = 4096; size = (1 << (fls(size) - 1)); - val = pci_read_config(dev, cap + PCIR_EXPRESS_DEVICE_CTL, 2); - val &= ~PCIM_EXP_CTL_MAX_READ_REQUEST; + val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); + val &= ~PCIEM_CTL_MAX_READ_REQUEST; val |= (fls(size) - 8) << 12; - pci_write_config(dev, cap + PCIR_EXPRESS_DEVICE_CTL, val, 2); + pci_write_config(dev, cap + PCIER_DEVICE_CTL, val, 2); return (size); } Modified: stable/9/sys/dev/pci/pcireg.h ============================================================================== --- stable/9/sys/dev/pci/pcireg.h Wed Oct 24 18:36:41 2012 (r242014) +++ stable/9/sys/dev/pci/pcireg.h Wed Oct 24 19:04:17 2012 (r242015) @@ -620,56 +620,258 @@ #define PCIR_SUBVENDCAP_ID 0x4 /* PCI Express definitions */ -#define PCIR_EXPRESS_FLAGS 0x2 -#define PCIM_EXP_FLAGS_VERSION 0x000F -#define PCIM_EXP_FLAGS_TYPE 0x00F0 -#define PCIM_EXP_TYPE_ENDPOINT 0x0000 -#define PCIM_EXP_TYPE_LEGACY_ENDPOINT 0x0010 -#define PCIM_EXP_TYPE_ROOT_PORT 0x0040 -#define PCIM_EXP_TYPE_UPSTREAM_PORT 0x0050 -#define PCIM_EXP_TYPE_DOWNSTREAM_PORT 0x0060 -#define PCIM_EXP_TYPE_PCI_BRIDGE 0x0070 -#define PCIM_EXP_TYPE_PCIE_BRIDGE 0x0080 -#define PCIM_EXP_TYPE_ROOT_INT_EP 0x0090 -#define PCIM_EXP_TYPE_ROOT_EC 0x00a0 -#define PCIM_EXP_FLAGS_SLOT 0x0100 -#define PCIM_EXP_FLAGS_IRQ 0x3e00 -#define PCIR_EXPRESS_DEVICE_CAP 0x4 -#define PCIM_EXP_CAP_MAX_PAYLOAD 0x0007 -#define PCIR_EXPRESS_DEVICE_CTL 0x8 -#define PCIM_EXP_CTL_NFER_ENABLE 0x0002 -#define PCIM_EXP_CTL_FER_ENABLE 0x0004 -#define PCIM_EXP_CTL_URR_ENABLE 0x0008 -#define PCIM_EXP_CTL_RELAXED_ORD_ENABLE 0x0010 -#define PCIM_EXP_CTL_MAX_PAYLOAD 0x00e0 -#define PCIM_EXP_CTL_NOSNOOP_ENABLE 0x0800 -#define PCIM_EXP_CTL_MAX_READ_REQUEST 0x7000 -#define PCIR_EXPRESS_DEVICE_STA 0xa -#define PCIM_EXP_STA_CORRECTABLE_ERROR 0x0001 -#define PCIM_EXP_STA_NON_FATAL_ERROR 0x0002 -#define PCIM_EXP_STA_FATAL_ERROR 0x0004 -#define PCIM_EXP_STA_UNSUPPORTED_REQ 0x0008 -#define PCIM_EXP_STA_AUX_POWER 0x0010 -#define PCIM_EXP_STA_TRANSACTION_PND 0x0020 -#define PCIR_EXPRESS_LINK_CAP 0xc -#define PCIM_LINK_CAP_MAX_SPEED 0x0000000f -#define PCIM_LINK_CAP_MAX_WIDTH 0x000003f0 -#define PCIM_LINK_CAP_ASPM 0x00000c00 -#define PCIM_LINK_CAP_L0S_EXIT 0x00007000 -#define PCIM_LINK_CAP_L1_EXIT 0x00038000 -#define PCIM_LINK_CAP_PORT 0xff000000 -#define PCIR_EXPRESS_LINK_CTL 0x10 -#define PCIR_EXPRESS_LINK_STA 0x12 -#define PCIM_LINK_STA_SPEED 0x000f -#define PCIM_LINK_STA_WIDTH 0x03f0 -#define PCIM_LINK_STA_TRAINING_ERROR 0x0400 -#define PCIM_LINK_STA_TRAINING 0x0800 -#define PCIM_LINK_STA_SLOT_CLOCK 0x1000 -#define PCIR_EXPRESS_SLOT_CAP 0x14 -#define PCIR_EXPRESS_SLOT_CTL 0x18 -#define PCIR_EXPRESS_SLOT_STA 0x1a -#define PCIR_EXPRESS_ROOT_CTL 0x1c -#define PCIR_EXPRESS_ROOT_STA 0x20 +#define PCIER_FLAGS 0x2 +#define PCIEM_FLAGS_VERSION 0x000F +#define PCIEM_FLAGS_TYPE 0x00F0 +#define PCIEM_TYPE_ENDPOINT 0x0000 +#define PCIEM_TYPE_LEGACY_ENDPOINT 0x0010 +#define PCIEM_TYPE_ROOT_PORT 0x0040 +#define PCIEM_TYPE_UPSTREAM_PORT 0x0050 +#define PCIEM_TYPE_DOWNSTREAM_PORT 0x0060 +#define PCIEM_TYPE_PCI_BRIDGE 0x0070 +#define PCIEM_TYPE_PCIE_BRIDGE 0x0080 +#define PCIEM_TYPE_ROOT_INT_EP 0x0090 +#define PCIEM_TYPE_ROOT_EC 0x00a0 +#define PCIEM_FLAGS_SLOT 0x0100 +#define PCIEM_FLAGS_IRQ 0x3e00 +#define PCIER_DEVICE_CAP 0x4 +#define PCIEM_CAP_MAX_PAYLOAD 0x00000007 +#define PCIEM_CAP_PHANTHOM_FUNCS 0x00000018 +#define PCIEM_CAP_EXT_TAG_FIELD 0x00000020 +#define PCIEM_CAP_L0S_LATENCY 0x000001c0 +#define PCIEM_CAP_L1_LATENCY 0x00000e00 +#define PCIEM_CAP_ROLE_ERR_RPT 0x00008000 +#define PCIEM_CAP_SLOT_PWR_LIM_VAL 0x03fc0000 +#define PCIEM_CAP_SLOT_PWR_LIM_SCALE 0x0c000000 +#define PCIEM_CAP_FLR 0x10000000 +#define PCIER_DEVICE_CTL 0x8 +#define PCIEM_CTL_COR_ENABLE 0x0001 +#define PCIEM_CTL_NFER_ENABLE 0x0002 +#define PCIEM_CTL_FER_ENABLE 0x0004 +#define PCIEM_CTL_URR_ENABLE 0x0008 +#define PCIEM_CTL_RELAXED_ORD_ENABLE 0x0010 +#define PCIEM_CTL_MAX_PAYLOAD 0x00e0 +#define PCIEM_CTL_EXT_TAG_FIELD 0x0100 +#define PCIEM_CTL_PHANTHOM_FUNCS 0x0200 +#define PCIEM_CTL_AUX_POWER_PM 0x0400 +#define PCIEM_CTL_NOSNOOP_ENABLE 0x0800 +#define PCIEM_CTL_MAX_READ_REQUEST 0x7000 +#define PCIEM_CTL_BRDG_CFG_RETRY 0x8000 /* PCI-E - PCI/PCI-X bridges */ +#define PCIEM_CTL_INITIATE_FLR 0x8000 /* FLR capable endpoints */ +#define PCIER_DEVICE_STA 0xa +#define PCIEM_STA_CORRECTABLE_ERROR 0x0001 +#define PCIEM_STA_NON_FATAL_ERROR 0x0002 +#define PCIEM_STA_FATAL_ERROR 0x0004 +#define PCIEM_STA_UNSUPPORTED_REQ 0x0008 +#define PCIEM_STA_AUX_POWER 0x0010 +#define PCIEM_STA_TRANSACTION_PND 0x0020 +#define PCIER_LINK_CAP 0xc +#define PCIEM_LINK_CAP_MAX_SPEED 0x0000000f +#define PCIEM_LINK_CAP_MAX_WIDTH 0x000003f0 +#define PCIEM_LINK_CAP_ASPM 0x00000c00 +#define PCIEM_LINK_CAP_L0S_EXIT 0x00007000 +#define PCIEM_LINK_CAP_L1_EXIT 0x00038000 +#define PCIEM_LINK_CAP_CLOCK_PM 0x00040000 +#define PCIEM_LINK_CAP_SURPRISE_DOWN 0x00080000 +#define PCIEM_LINK_CAP_DL_ACTIVE 0x00100000 +#define PCIEM_LINK_CAP_LINK_BW_NOTIFY 0x00200000 +#define PCIEM_LINK_CAP_ASPM_COMPLIANCE 0x00400000 +#define PCIEM_LINK_CAP_PORT 0xff000000 +#define PCIER_LINK_CTL 0x10 +#define PCIEM_LINK_CTL_ASPMC_DIS 0x0000 +#define PCIEM_LINK_CTL_ASPMC_L0S 0x0001 +#define PCIEM_LINK_CTL_ASPMC_L1 0x0002 +#define PCIEM_LINK_CTL_ASPMC 0x0003 +#define PCIEM_LINK_CTL_RCB 0x0008 +#define PCIEM_LINK_CTL_LINK_DIS 0x0010 +#define PCIEM_LINK_CTL_RETRAIN_LINK 0x0020 +#define PCIEM_LINK_CTL_COMMON_CLOCK 0x0040 +#define PCIEM_LINK_CTL_EXTENDED_SYNC 0x0080 +#define PCIEM_LINK_CTL_ECPM 0x0100 +#define PCIEM_LINK_CTL_HAWD 0x0200 +#define PCIEM_LINK_CTL_LBMIE 0x0400 +#define PCIEM_LINK_CTL_LABIE 0x0800 +#define PCIER_LINK_STA 0x12 +#define PCIEM_LINK_STA_SPEED 0x000f +#define PCIEM_LINK_STA_WIDTH 0x03f0 +#define PCIEM_LINK_STA_TRAINING_ERROR 0x0400 +#define PCIEM_LINK_STA_TRAINING 0x0800 +#define PCIEM_LINK_STA_SLOT_CLOCK 0x1000 +#define PCIEM_LINK_STA_DL_ACTIVE 0x2000 +#define PCIEM_LINK_STA_LINK_BW_MGMT 0x4000 +#define PCIEM_LINK_STA_LINK_AUTO_BW 0x8000 +#define PCIER_SLOT_CAP 0x14 +#define PCIEM_SLOT_CAP_APB 0x00000001 +#define PCIEM_SLOT_CAP_PCP 0x00000002 +#define PCIEM_SLOT_CAP_MRLSP 0x00000004 +#define PCIEM_SLOT_CAP_AIP 0x00000008 +#define PCIEM_SLOT_CAP_PIP 0x00000010 +#define PCIEM_SLOT_CAP_HPS 0x00000020 +#define PCIEM_SLOT_CAP_HPC 0x00000040 +#define PCIEM_SLOT_CAP_SPLV 0x00007f80 +#define PCIEM_SLOT_CAP_SPLS 0x00018000 +#define PCIEM_SLOT_CAP_EIP 0x00020000 +#define PCIEM_SLOT_CAP_NCCS 0x00040000 +#define PCIEM_SLOT_CAP_PSN 0xfff80000 +#define PCIER_SLOT_CTL 0x18 +#define PCIEM_SLOT_CTL_ABPE 0x0001 +#define PCIEM_SLOT_CTL_PFDE 0x0002 +#define PCIEM_SLOT_CTL_MRLSCE 0x0004 +#define PCIEM_SLOT_CTL_PDCE 0x0008 +#define PCIEM_SLOT_CTL_CCIE 0x0010 +#define PCIEM_SLOT_CTL_HPIE 0x0020 +#define PCIEM_SLOT_CTL_AIC 0x00c0 +#define PCIEM_SLOT_CTL_PIC 0x0300 +#define PCIEM_SLOT_CTL_PCC 0x0400 +#define PCIEM_SLOT_CTL_EIC 0x0800 +#define PCIEM_SLOT_CTL_DLLSCE 0x1000 +#define PCIER_SLOT_STA 0x1a +#define PCIEM_SLOT_STA_ABP 0x0001 +#define PCIEM_SLOT_STA_PFD 0x0002 +#define PCIEM_SLOT_STA_MRLSC 0x0004 +#define PCIEM_SLOT_STA_PDC 0x0008 +#define PCIEM_SLOT_STA_CC 0x0010 +#define PCIEM_SLOT_STA_MRLSS 0x0020 +#define PCIEM_SLOT_STA_PDS 0x0040 +#define PCIEM_SLOT_STA_EIS 0x0080 +#define PCIEM_SLOT_STA_DLLSC 0x0100 +#define PCIER_ROOT_CTL 0x1c +#define PCIER_ROOT_CAP 0x1e +#define PCIER_ROOT_STA 0x20 +#define PCIER_DEVICE_CAP2 0x24 +#define PCIER_DEVICE_CTL2 0x28 +#define PCIEM_CTL2_COMP_TIMEOUT_VAL 0x000f +#define PCIEM_CTL2_COMP_TIMEOUT_DIS 0x0010 +#define PCIEM_CTL2_ARI 0x0020 +#define PCIEM_CTL2_ATOMIC_REQ_ENABLE 0x0040 +#define PCIEM_CTL2_ATOMIC_EGR_BLOCK 0x0080 +#define PCIEM_CTL2_ID_ORDERED_REQ_EN 0x0100 +#define PCIEM_CTL2_ID_ORDERED_CMP_EN 0x0200 +#define PCIEM_CTL2_LTR_ENABLE 0x0400 +#define PCIEM_CTL2_OBFF 0x6000 +#define PCIEM_OBFF_DISABLE 0x0000 +#define PCIEM_OBFF_MSGA_ENABLE 0x2000 +#define PCIEM_OBFF_MSGB_ENABLE 0x4000 +#define PCIEM_OBFF_WAKE_ENABLE 0x6000 +#define PCIEM_CTL2_END2END_TLP 0x8000 +#define PCIER_DEVICE_STA2 0x2a +#define PCIER_LINK_CAP2 0x2c +#define PCIER_LINK_CTL2 0x30 +#define PCIER_LINK_STA2 0x32 +#define PCIER_SLOT_CAP2 0x34 +#define PCIER_SLOT_CTL2 0x38 +#define PCIER_SLOT_STA2 0x3a + +/* Old compatibility definitions for PCI Express registers */ +#define PCIR_EXPRESS_FLAGS PCIER_FLAGS +#define PCIM_EXP_FLAGS_VERSION PCIEM_FLAGS_VERSION +#define PCIM_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE +#define PCIM_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT +#define PCIM_EXP_TYPE_LEGACY_ENDPOINT PCIEM_TYPE_LEGACY_ENDPOINT +#define PCIM_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT +#define PCIM_EXP_TYPE_UPSTREAM_PORT PCIEM_TYPE_UPSTREAM_PORT +#define PCIM_EXP_TYPE_DOWNSTREAM_PORT PCIEM_TYPE_DOWNSTREAM_PORT +#define PCIM_EXP_TYPE_PCI_BRIDGE PCIEM_TYPE_PCI_BRIDGE +#define PCIM_EXP_TYPE_PCIE_BRIDGE PCIEM_TYPE_PCIE_BRIDGE +#define PCIM_EXP_TYPE_ROOT_INT_EP PCIEM_TYPE_ROOT_INT_EP +#define PCIM_EXP_TYPE_ROOT_EC PCIEM_TYPE_ROOT_EC +#define PCIM_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT +#define PCIM_EXP_FLAGS_IRQ PCIEM_FLAGS_IRQ +#define PCIR_EXPRESS_DEVICE_CAP PCIER_DEVICE_CAP +#define PCIM_EXP_CAP_MAX_PAYLOAD PCIEM_CAP_MAX_PAYLOAD +#define PCIM_EXP_CAP_PHANTHOM_FUNCS PCIEM_CAP_PHANTHOM_FUNCS +#define PCIM_EXP_CAP_EXT_TAG_FIELD PCIEM_CAP_EXT_TAG_FIELD +#define PCIM_EXP_CAP_L0S_LATENCY PCIEM_CAP_L0S_LATENCY +#define PCIM_EXP_CAP_L1_LATENCY PCIEM_CAP_L1_LATENCY +#define PCIM_EXP_CAP_ROLE_ERR_RPT PCIEM_CAP_ROLE_ERR_RPT +#define PCIM_EXP_CAP_SLOT_PWR_LIM_VAL PCIEM_CAP_SLOT_PWR_LIM_VAL +#define PCIM_EXP_CAP_SLOT_PWR_LIM_SCALE PCIEM_CAP_SLOT_PWR_LIM_SCALE +#define PCIM_EXP_CAP_FLR PCIEM_CAP_FLR +#define PCIR_EXPRESS_DEVICE_CTL PCIER_DEVICE_CTL +#define PCIM_EXP_CTL_COR_ENABLE PCIEM_CTL_COR_ENABLE +#define PCIM_EXP_CTL_NFER_ENABLE PCIEM_CTL_NFER_ENABLE +#define PCIM_EXP_CTL_FER_ENABLE PCIEM_CTL_FER_ENABLE +#define PCIM_EXP_CTL_URR_ENABLE PCIEM_CTL_URR_ENABLE +#define PCIM_EXP_CTL_RELAXED_ORD_ENABLE PCIEM_CTL_RELAXED_ORD_ENABLE +#define PCIM_EXP_CTL_MAX_PAYLOAD PCIEM_CTL_MAX_PAYLOAD +#define PCIM_EXP_CTL_EXT_TAG_FIELD PCIEM_CTL_EXT_TAG_FIELD +#define PCIM_EXP_CTL_PHANTHOM_FUNCS PCIEM_CTL_PHANTHOM_FUNCS +#define PCIM_EXP_CTL_AUX_POWER_PM PCIEM_CTL_AUX_POWER_PM +#define PCIM_EXP_CTL_NOSNOOP_ENABLE PCIEM_CTL_NOSNOOP_ENABLE +#define PCIM_EXP_CTL_MAX_READ_REQUEST PCIEM_CTL_MAX_READ_REQUEST +#define PCIM_EXP_CTL_BRDG_CFG_RETRY PCIEM_CTL_BRDG_CFG_RETRY +#define PCIM_EXP_CTL_INITIATE_FLR PCIEM_CTL_INITIATE_FLR +#define PCIR_EXPRESS_DEVICE_STA PCIER_DEVICE_STA +#define PCIM_EXP_STA_CORRECTABLE_ERROR PCIEM_STA_CORRECTABLE_ERROR +#define PCIM_EXP_STA_NON_FATAL_ERROR PCIEM_STA_NON_FATAL_ERROR +#define PCIM_EXP_STA_FATAL_ERROR PCIEM_STA_FATAL_ERROR +#define PCIM_EXP_STA_UNSUPPORTED_REQ PCIEM_STA_UNSUPPORTED_REQ +#define PCIM_EXP_STA_AUX_POWER PCIEM_STA_AUX_POWER +#define PCIM_EXP_STA_TRANSACTION_PND PCIEM_STA_TRANSACTION_PND +#define PCIR_EXPRESS_LINK_CAP PCIER_LINK_CAP +#define PCIM_LINK_CAP_MAX_SPEED PCIEM_LINK_CAP_MAX_SPEED +#define PCIM_LINK_CAP_MAX_WIDTH PCIEM_LINK_CAP_MAX_WIDTH +#define PCIM_LINK_CAP_ASPM PCIEM_LINK_CAP_ASPM +#define PCIM_LINK_CAP_L0S_EXIT PCIEM_LINK_CAP_L0S_EXIT +#define PCIM_LINK_CAP_L1_EXIT PCIEM_LINK_CAP_L1_EXIT +#define PCIM_LINK_CAP_CLOCK_PM PCIEM_LINK_CAP_CLOCK_PM +#define PCIM_LINK_CAP_SURPRISE_DOWN PCIEM_LINK_CAP_SURPRISE_DOWN +#define PCIM_LINK_CAP_DL_ACTIVE PCIEM_LINK_CAP_DL_ACTIVE +#define PCIM_LINK_CAP_LINK_BW_NOTIFY PCIEM_LINK_CAP_LINK_BW_NOTIFY +#define PCIM_LINK_CAP_ASPM_COMPLIANCE PCIEM_LINK_CAP_ASPM_COMPLIANCE +#define PCIM_LINK_CAP_PORT PCIEM_LINK_CAP_PORT +#define PCIR_EXPRESS_LINK_CTL PCIER_LINK_CTL +#define PCIM_EXP_LINK_CTL_ASPMC_DIS PCIEM_LINK_CTL_ASPMC_DIS +#define PCIM_EXP_LINK_CTL_ASPMC_L0S PCIEM_LINK_CTL_ASPMC_L0S +#define PCIM_EXP_LINK_CTL_ASPMC_L1 PCIEM_LINK_CTL_ASPMC_L1 +#define PCIM_EXP_LINK_CTL_ASPMC PCIEM_LINK_CTL_ASPMC +#define PCIM_EXP_LINK_CTL_RCB PCIEM_LINK_CTL_RCB +#define PCIM_EXP_LINK_CTL_LINK_DIS PCIEM_LINK_CTL_LINK_DIS +#define PCIM_EXP_LINK_CTL_RETRAIN_LINK PCIEM_LINK_CTL_RETRAIN_LINK +#define PCIM_EXP_LINK_CTL_COMMON_CLOCK PCIEM_LINK_CTL_COMMON_CLOCK +#define PCIM_EXP_LINK_CTL_EXTENDED_SYNC PCIEM_LINK_CTL_EXTENDED_SYNC +#define PCIM_EXP_LINK_CTL_ECPM PCIEM_LINK_CTL_ECPM +#define PCIM_EXP_LINK_CTL_HAWD PCIEM_LINK_CTL_HAWD +#define PCIM_EXP_LINK_CTL_LBMIE PCIEM_LINK_CTL_LBMIE +#define PCIM_EXP_LINK_CTL_LABIE PCIEM_LINK_CTL_LABIE +#define PCIR_EXPRESS_LINK_STA PCIER_LINK_STA +#define PCIM_LINK_STA_SPEED PCIEM_LINK_STA_SPEED +#define PCIM_LINK_STA_WIDTH PCIEM_LINK_STA_WIDTH +#define PCIM_LINK_STA_TRAINING_ERROR PCIEM_LINK_STA_TRAINING_ERROR +#define PCIM_LINK_STA_TRAINING PCIEM_LINK_STA_TRAINING +#define PCIM_LINK_STA_SLOT_CLOCK PCIEM_LINK_STA_SLOT_CLOCK +#define PCIM_LINK_STA_DL_ACTIVE PCIEM_LINK_STA_DL_ACTIVE +#define PCIM_LINK_STA_LINK_BW_MGMT PCIEM_LINK_STA_LINK_BW_MGMT +#define PCIM_LINK_STA_LINK_AUTO_BW PCIEM_LINK_STA_LINK_AUTO_BW +#define PCIR_EXPRESS_SLOT_CAP PCIER_SLOT_CAP +#define PCIR_EXPRESS_SLOT_CTL PCIER_SLOT_CTL +#define PCIR_EXPRESS_SLOT_STA PCIER_SLOT_STA +#define PCIR_EXPRESS_ROOT_CTL PCIER_ROOT_CTL +#define PCIR_EXPRESS_ROOT_CAP PCIER_ROOT_CAP +#define PCIR_EXPRESS_ROOT_STA PCIER_ROOT_STA +#define PCIR_EXPRESS_DEVICE_CAP2 PCIER_DEVICE_CAP2 +#define PCIR_EXPRESS_DEVICE_CTL2 PCIER_DEVICE_CTL2 +#define PCIM_EXP_CTL2_COMP_TIMEOUT_VAL PCIEM_CTL2_COMP_TIMEOUT_VAL +#define PCIM_EXP_CTL2_COMP_TIMEOUT_DIS PCIEM_CTL2_COMP_TIMEOUT_DIS +#define PCIM_EXP_CTL2_ARI PCIEM_CTL2_ARI +#define PCIM_EXP_CTL2_ATOMIC_REQ_ENABLE PCIEM_CTL2_ATOMIC_REQ_ENABLE +#define PCIM_EXP_CTL2_ATOMIC_EGR_BLOCK PCIEM_CTL2_ATOMIC_EGR_BLOCK +#define PCIM_EXP_CTL2_ID_ORDERED_REQ_EN PCIEM_CTL2_ID_ORDERED_REQ_EN +#define PCIM_EXP_CTL2_ID_ORDERED_CMP_EN PCIEM_CTL2_ID_ORDERED_CMP_EN +#define PCIM_EXP_CTL2_LTR_ENABLE PCIEM_CTL2_LTR_ENABLE +#define PCIM_EXP_CTL2_OBFF PCIEM_CTL2_OBFF +#define PCIM_EXP_OBFF_DISABLE PCIEM_OBFF_DISABLE +#define PCIM_EXP_OBFF_MSGA_ENABLE PCIEM_OBFF_MSGA_ENABLE +#define PCIM_EXP_OBFF_MSGB_ENABLE PCIEM_OBFF_MSGB_ENABLE +#define PCIM_EXP_OBFF_WAKE_ENABLE PCIEM_OBFF_WAKE_ENABLE +#define PCIM_EXP_CTL2_END2END_TLP PCIEM_CTL2_END2END_TLP +#define PCIR_EXPRESS_DEVICE_STA2 PCIER_DEVICE_STA2 +#define PCIR_EXPRESS_LINK_CAP2 PCIER_LINK_CAP2 +#define PCIR_EXPRESS_LINK_CTL2 PCIER_LINK_CTL2 +#define PCIR_EXPRESS_LINK_STA2 PCIER_LINK_STA2 +#define PCIR_EXPRESS_SLOT_CAP2 PCIER_SLOT_CAP2 +#define PCIR_EXPRESS_SLOT_CTL2 PCIER_SLOT_CTL2 +#define PCIR_EXPRESS_SLOT_STA2 PCIER_SLOT_STA2 /* MSI-X definitions */ #define PCIR_MSIX_CTRL 0x2 Modified: stable/9/sys/dev/re/if_re.c ============================================================================== --- stable/9/sys/dev/re/if_re.c Wed Oct 24 18:36:41 2012 (r242014) +++ stable/9/sys/dev/re/if_re.c Wed Oct 24 19:04:17 2012 (r242015) @@ -1343,14 +1343,14 @@ re_attach(device_t dev) /* Disable ASPM L0S/L1. */ if (sc->rl_expcap != 0) { cap = pci_read_config(dev, sc->rl_expcap + - PCIR_EXPRESS_LINK_CAP, 2); - if ((cap & PCIM_LINK_CAP_ASPM) != 0) { + PCIER_LINK_CAP, 2); + if ((cap & PCIEM_LINK_CAP_ASPM) != 0) { ctl = pci_read_config(dev, sc->rl_expcap + - PCIR_EXPRESS_LINK_CTL, 2); + PCIER_LINK_CTL, 2); if ((ctl & 0x0003) != 0) { ctl &= ~0x0003; pci_write_config(dev, sc->rl_expcap + - PCIR_EXPRESS_LINK_CTL, ctl, 2); + PCIER_LINK_CTL, ctl, 2); device_printf(dev, "ASPM disabled\n"); } } else Modified: stable/9/sys/ofed/include/linux/pci.h ============================================================================== --- stable/9/sys/ofed/include/linux/pci.h Wed Oct 24 18:36:41 2012 (r242014) +++ stable/9/sys/ofed/include/linux/pci.h Wed Oct 24 19:04:17 2012 (r242015) @@ -82,8 +82,8 @@ struct pci_device_id { #define PCI_VENDOR_ID PCIR_DEVVENDOR #define PCI_COMMAND PCIR_COMMAND -#define PCI_EXP_DEVCTL PCIR_EXPRESS_DEVICE_CTL -#define PCI_EXP_LNKCTL PCIR_EXPRESS_LINK_CTL +#define PCI_EXP_DEVCTL PCIER_DEVICE_CTL +#define PCI_EXP_LNKCTL PCIER_LINK_CTL #define IORESOURCE_MEM SYS_RES_MEMORY #define IORESOURCE_IO SYS_RES_IOPORT Modified: stable/9/sys/powerpc/mpc85xx/pci_fdt.c ============================================================================== --- stable/9/sys/powerpc/mpc85xx/pci_fdt.c Wed Oct 24 18:36:41 2012 (r242014) +++ stable/9/sys/powerpc/mpc85xx/pci_fdt.c Wed Oct 24 19:04:17 2012 (r242015) @@ -843,10 +843,10 @@ fsl_pcib_err_init(device_t dev) 0xffffffff); dsr = fsl_pcib_cfgread(sc, 0, 0, 0, - sc->sc_pcie_capreg + PCIR_EXPRESS_DEVICE_STA, 2); + sc->sc_pcie_capreg + PCIER_DEVICE_STA, 2); if (dsr) fsl_pcib_cfgwrite(sc, 0, 0, 0, - sc->sc_pcie_capreg + PCIR_EXPRESS_DEVICE_STA, + sc->sc_pcie_capreg + PCIER_DEVICE_STA, 0xffff, 2); /* Enable all errors reporting */ @@ -856,11 +856,11 @@ fsl_pcib_err_init(device_t dev) /* Enable error reporting: URR, FER, NFER */ dcr = fsl_pcib_cfgread(sc, 0, 0, 0, - sc->sc_pcie_capreg + PCIR_EXPRESS_DEVICE_CTL, 4); - dcr |= PCIM_EXP_CTL_URR_ENABLE | PCIM_EXP_CTL_FER_ENABLE | - PCIM_EXP_CTL_NFER_ENABLE; + sc->sc_pcie_capreg + PCIER_DEVICE_CTL, 4); + dcr |= PCIEM_CTL_URR_ENABLE | PCIEM_CTL_FER_ENABLE | + PCIEM_CTL_NFER_ENABLE; fsl_pcib_cfgwrite(sc, 0, 0, 0, - sc->sc_pcie_capreg + PCIR_EXPRESS_DEVICE_CTL, dcr, 4); + sc->sc_pcie_capreg + PCIER_DEVICE_CTL, dcr, 4); } }