From nobody Fri Jun 20 13:52:33 2025 X-Original-To: dev-commits-src-all@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4bNzSL1QJbz5y4MB; Fri, 20 Jun 2025 13:52:34 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R11" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4bNzSK51tTz3Y2W; Fri, 20 Jun 2025 13:52:33 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1750427553; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=dud0TXrdiEm54tSRGJxiB4td52JWeUtnvClLsqbfkro=; b=wtBh9TU8f6NYs3NCXbWMEbZ79Y9M5zm7YmEGbfSuYallPLGaiyn9Mubk/vjPRzgeQHVwkd WWcwUynn6GIdJLGZdX+ij07YAOqx1Gs2wek/sbcMeQqrOeMoAvLECmXCuXwVwyJRxbHn4P bs/2zssHHXU38ikRb7Gb+AKJKG1kNnr/Qt+oEkF+XUFhlFZnQA6cZ03nWmgqzmMm37BhaA sayNBMwAkrSo9XsjMfGoHXz1NDndfDheFq2RzgIH86xqiFxSGe22CsTrkv2zf8I9cWXnOT G4VfUS7qyls0Z7f5GxKHzcqnp8nTbSQnYqbyPS95EupD3rsoXqWS+Co7jeNovg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1750427553; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=dud0TXrdiEm54tSRGJxiB4td52JWeUtnvClLsqbfkro=; b=c0MmVGeb3Avc93BanD330mPeTwA0llxeNUZixpfNYDngCPtcG6jSZ/STdsVQXO+jFxLvtX 9akoSwg1tsvdz8uOCQIVzdAEFExNtnGAh/pMokWZVtFCkbrakJz2l/F/ChO56Z8B3mAfi6 nGtIP+3pgrHG1/73MV4vFo/uNwYQn5V/R8EoBV5RdCLT0ETUuS7iSCiKpx/jGfEOlHg2uu UeR4TMUmdZ1rqYYSasHl8OkvKkyULiqpRAPUVIbG1aiUKtGpHSxzjMCONFS/y3eE07ioYR TEQwhIEFQ4V3mNAK/uAjDF4JCmX+WDA5RsMOZRm5ZKG7+WZb7pxZoelhvK+KWw== ARC-Authentication-Results: i=1; mx1.freebsd.org; none ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1750427553; a=rsa-sha256; cv=none; b=tggj7AjEyR+RAIP50+mFS5hTrbj0rXEchONDixNC3rkJo9Ls5Tr41UKNeSACEXnTgjouWG rNE+6h1m3N93JhFoh70t2/jlJPzremS9aCQ0UjB+jK+dHjOKQABrBcRYzqR8kbucJFum5M t8lRXovcm1hsSXvCxNChKR3oArzpnhJkGAex88pWl68SFS7GxaE5YM+x0Hf+WiDmAVfHpa oTlzZGwTobfVVqqZDgIcyKtVN1stZ6Ul+8uMMywmQ3nde2U0epGW26WSvFCkC02C6kNOvv 7RCKHk+1pJ+ZQJ5PkzVLTLoFLxpNNHtiNVEJVLcHLY/U1bEFcbXZWc2sCVClRg== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 4bNzSK4LYrzp78; Fri, 20 Jun 2025 13:52:33 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.18.1/8.18.1) with ESMTP id 55KDqXAX058368; Fri, 20 Jun 2025 13:52:33 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.18.1/8.18.1/Submit) id 55KDqXHE058365; Fri, 20 Jun 2025 13:52:33 GMT (envelope-from git) Date: Fri, 20 Jun 2025 13:52:33 GMT Message-Id: <202506201352.55KDqXHE058365@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-branches@FreeBSD.org From: Mark Johnston Subject: git: 8de50b4e29ef - stable/14 - qat: update 4xxx capabilities handling List-Id: Commit messages for all branches of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-all List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-BeenThere: dev-commits-src-all@freebsd.org Sender: owner-dev-commits-src-all@FreeBSD.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: markj X-Git-Repository: src X-Git-Refname: refs/heads/stable/14 X-Git-Reftype: branch X-Git-Commit: 8de50b4e29ef7496e99597ebbd64bfb6e16dc364 Auto-Submitted: auto-generated The branch stable/14 has been updated by markj: URL: https://cgit.FreeBSD.org/src/commit/?id=8de50b4e29ef7496e99597ebbd64bfb6e16dc364 commit 8de50b4e29ef7496e99597ebbd64bfb6e16dc364 Author: Hareshx Sankar Raj AuthorDate: 2025-04-30 19:48:44 +0000 Commit: Mark Johnston CommitDate: 2025-06-20 12:47:27 +0000 qat: update 4xxx capabilities handling Some capabilities were not properly fused out based on the hardware slices. Hence updated the function accordingly. Both PF and VF are changed. This change also streamlines capability handling for SYM service: - Lack of UCS slice does not mean that CIPHER capabilities are not available. - SYM capabilities should be considered disabled only if both AUTH and CIPHER capabilities are not present. - AUTH capability shouldn't disable CIPHER. SMX slice mask for qat_4xxx is also corrected to check for both SM3 and SM4 support. Reviewed by: markj, ziaee MFC after: 2 weeks Sponsored by: Intel Corporation Differential Revision: https://reviews.freebsd.org/D50379 (cherry picked from commit 4da5c15e5c84738903fd306b54b18a0aaf166d5f) --- sys/dev/qat/qat_hw/qat_4xxx/adf_4xxx_hw_data.c | 98 +++++++++++++--------- sys/dev/qat/qat_hw/qat_4xxx/adf_4xxx_hw_data.h | 4 +- sys/dev/qat/qat_hw/qat_4xxxvf/adf_4xxxvf_hw_data.c | 89 +++++++++++++------- sys/dev/qat/qat_hw/qat_4xxxvf/adf_4xxxvf_hw_data.h | 14 +++- 4 files changed, 133 insertions(+), 72 deletions(-) diff --git a/sys/dev/qat/qat_hw/qat_4xxx/adf_4xxx_hw_data.c b/sys/dev/qat/qat_hw/qat_4xxx/adf_4xxx_hw_data.c index 43e530c3a6f1..9a84ad652282 100644 --- a/sys/dev/qat/qat_hw/qat_4xxx/adf_4xxx_hw_data.c +++ b/sys/dev/qat/qat_hw/qat_4xxx/adf_4xxx_hw_data.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause */ -/* Copyright(c) 2007-2022 Intel Corporation */ +/* Copyright(c) 2007-2025 Intel Corporation */ #include #include #include @@ -212,57 +212,77 @@ adf_4xxx_get_hw_cap(struct adf_accel_dev *accel_dev) { device_t pdev = accel_dev->accel_pci_dev.pci_dev; u32 fusectl1; - u32 capabilities; + u32 capabilities_sym, capabilities_sym_cipher, capabilities_sym_auth, + capabilities_asym, capabilities_dc, capabilities_other; + + capabilities_other = ICP_ACCEL_CAPABILITIES_RL; /* Read accelerator capabilities mask */ fusectl1 = pci_read_config(pdev, ADF_4XXX_FUSECTL1_OFFSET, 4); - capabilities = ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC | - ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC | - ICP_ACCEL_CAPABILITIES_CIPHER | - ICP_ACCEL_CAPABILITIES_AUTHENTICATION | - ICP_ACCEL_CAPABILITIES_COMPRESSION | - ICP_ACCEL_CAPABILITIES_LZ4_COMPRESSION | - ICP_ACCEL_CAPABILITIES_LZ4S_COMPRESSION | - ICP_ACCEL_CAPABILITIES_SHA3 | ICP_ACCEL_CAPABILITIES_HKDF | - ICP_ACCEL_CAPABILITIES_SHA3_EXT | ICP_ACCEL_CAPABILITIES_SM3 | + + capabilities_sym_cipher = ICP_ACCEL_CAPABILITIES_HKDF | ICP_ACCEL_CAPABILITIES_SM4 | ICP_ACCEL_CAPABILITIES_CHACHA_POLY | - ICP_ACCEL_CAPABILITIES_AESGCM_SPC | ICP_ACCEL_CAPABILITIES_AES_V2 | - ICP_ACCEL_CAPABILITIES_RL | ICP_ACCEL_CAPABILITIES_ECEDMONT | - ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY64; + ICP_ACCEL_CAPABILITIES_AESGCM_SPC | ICP_ACCEL_CAPABILITIES_AES_V2; + capabilities_sym_auth = ICP_ACCEL_CAPABILITIES_SM3 | + ICP_ACCEL_CAPABILITIES_SHA3 | ICP_ACCEL_CAPABILITIES_SHA3_EXT; + /* A set bit in fusectl1 means the feature is OFF in this SKU */ if (fusectl1 & ICP_ACCEL_4XXX_MASK_CIPHER_SLICE) { - capabilities &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC; - capabilities &= ~ICP_ACCEL_CAPABILITIES_HKDF; - capabilities &= ~ICP_ACCEL_CAPABILITIES_CIPHER; - } - if (fusectl1 & ICP_ACCEL_4XXX_MASK_AUTH_SLICE) { - capabilities &= ~ICP_ACCEL_CAPABILITIES_AUTHENTICATION; - capabilities &= ~ICP_ACCEL_CAPABILITIES_SHA3; - capabilities &= ~ICP_ACCEL_CAPABILITIES_SHA3_EXT; - capabilities &= ~ICP_ACCEL_CAPABILITIES_CIPHER; + capabilities_sym_cipher &= ~ICP_ACCEL_CAPABILITIES_HKDF; + capabilities_sym_cipher &= ~ICP_ACCEL_CAPABILITIES_SM4; } - if (fusectl1 & ICP_ACCEL_MASK_PKE_SLICE) { - capabilities &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC; - capabilities &= ~ICP_ACCEL_CAPABILITIES_ECEDMONT; + + if (fusectl1 & ICP_ACCEL_4XXX_MASK_UCS_SLICE) { + capabilities_sym_cipher &= ~ICP_ACCEL_CAPABILITIES_CHACHA_POLY; + capabilities_sym_cipher &= ~ICP_ACCEL_CAPABILITIES_AESGCM_SPC; + capabilities_sym_cipher &= ~ICP_ACCEL_CAPABILITIES_AES_V2; } - if (fusectl1 & ICP_ACCEL_4XXX_MASK_COMPRESS_SLICE) { - capabilities &= ~ICP_ACCEL_CAPABILITIES_COMPRESSION; - capabilities &= ~ICP_ACCEL_CAPABILITIES_LZ4_COMPRESSION; - capabilities &= ~ICP_ACCEL_CAPABILITIES_LZ4S_COMPRESSION; - capabilities &= ~ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY64; + + if (fusectl1 & ICP_ACCEL_4XXX_MASK_AUTH_SLICE) { + capabilities_sym_auth &= ~ICP_ACCEL_CAPABILITIES_SM3; + capabilities_sym_auth &= ~ICP_ACCEL_CAPABILITIES_SHA3; + capabilities_sym_auth &= ~ICP_ACCEL_CAPABILITIES_SHA3_EXT; } + if (fusectl1 & ICP_ACCEL_4XXX_MASK_SMX_SLICE) { - capabilities &= ~ICP_ACCEL_CAPABILITIES_SM3; - capabilities &= ~ICP_ACCEL_CAPABILITIES_SM4; + capabilities_sym_cipher &= ~ICP_ACCEL_CAPABILITIES_SM4; + capabilities_sym_auth &= ~ICP_ACCEL_CAPABILITIES_SM3; } - if (fusectl1 & ICP_ACCEL_4XXX_MASK_UCS_SLICE) { - capabilities &= ~ICP_ACCEL_CAPABILITIES_CHACHA_POLY; - capabilities &= ~ICP_ACCEL_CAPABILITIES_AESGCM_SPC; - capabilities &= ~ICP_ACCEL_CAPABILITIES_AES_V2; - capabilities &= ~ICP_ACCEL_CAPABILITIES_CIPHER; + + if (capabilities_sym_cipher) + capabilities_sym_cipher |= ICP_ACCEL_CAPABILITIES_CIPHER; + + if (capabilities_sym_auth) + capabilities_sym_auth |= ICP_ACCEL_CAPABILITIES_AUTHENTICATION; + + capabilities_sym = capabilities_sym_cipher | capabilities_sym_auth; + + if (capabilities_sym) + capabilities_sym |= ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC; + + capabilities_asym = ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC | + ICP_ACCEL_CAPABILITIES_SM2 | ICP_ACCEL_CAPABILITIES_ECEDMONT; + + if (fusectl1 & ICP_ACCEL_4XXX_MASK_PKE_SLICE) { + capabilities_asym &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC; + capabilities_asym &= ~ICP_ACCEL_CAPABILITIES_SM2; + capabilities_asym &= ~ICP_ACCEL_CAPABILITIES_ECEDMONT; + } + + capabilities_dc = ICP_ACCEL_CAPABILITIES_COMPRESSION | + ICP_ACCEL_CAPABILITIES_LZ4_COMPRESSION | + ICP_ACCEL_CAPABILITIES_LZ4S_COMPRESSION | + ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY64; + + if (fusectl1 & ICP_ACCEL_4XXX_MASK_COMPRESS_SLICE) { + capabilities_dc &= ~ICP_ACCEL_CAPABILITIES_COMPRESSION; + capabilities_dc &= ~ICP_ACCEL_CAPABILITIES_LZ4_COMPRESSION; + capabilities_dc &= ~ICP_ACCEL_CAPABILITIES_LZ4S_COMPRESSION; + capabilities_dc &= ~ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY64; } - return capabilities; + return capabilities_sym | capabilities_dc | capabilities_asym | + capabilities_other; } static u32 diff --git a/sys/dev/qat/qat_hw/qat_4xxx/adf_4xxx_hw_data.h b/sys/dev/qat/qat_hw/qat_4xxx/adf_4xxx_hw_data.h index b6a5da92fdb5..c35ebbcadcd7 100644 --- a/sys/dev/qat/qat_hw/qat_4xxx/adf_4xxx_hw_data.h +++ b/sys/dev/qat/qat_hw/qat_4xxx/adf_4xxx_hw_data.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause */ -/* Copyright(c) 2007 - 2022 Intel Corporation */ +/* Copyright(c) 2007-2025 Intel Corporation */ #ifndef ADF_4XXX_HW_DATA_H_ #define ADF_4XXX_HW_DATA_H_ @@ -105,7 +105,7 @@ enum icp_qat_4xxx_slice_mask { ICP_ACCEL_4XXX_MASK_COMPRESS_SLICE = BIT(3), ICP_ACCEL_4XXX_MASK_UCS_SLICE = BIT(4), ICP_ACCEL_4XXX_MASK_EIA3_SLICE = BIT(5), - ICP_ACCEL_4XXX_MASK_SMX_SLICE = BIT(6), + ICP_ACCEL_4XXX_MASK_SMX_SLICE = BIT(7), }; void adf_init_hw_data_4xxx(struct adf_hw_device_data *hw_data, u32 id); diff --git a/sys/dev/qat/qat_hw/qat_4xxxvf/adf_4xxxvf_hw_data.c b/sys/dev/qat/qat_hw/qat_4xxxvf/adf_4xxxvf_hw_data.c index 27e5ef8162ab..f3d4ae3c7b38 100644 --- a/sys/dev/qat/qat_hw/qat_4xxxvf/adf_4xxxvf_hw_data.c +++ b/sys/dev/qat/qat_hw/qat_4xxxvf/adf_4xxxvf_hw_data.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause */ -/* Copyright(c) 2007-2022 Intel Corporation */ +/* Copyright(c) 2007-2025 Intel Corporation */ #include #include #include @@ -133,45 +133,74 @@ adf_4xxxvf_get_hw_cap(struct adf_accel_dev *accel_dev) { device_t pdev = accel_dev->accel_pci_dev.pci_dev; u32 vffusectl1; - u32 capabilities; - - capabilities = ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC + - ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC + - ICP_ACCEL_CAPABILITIES_CIPHER + - ICP_ACCEL_CAPABILITIES_AUTHENTICATION + - ICP_ACCEL_CAPABILITIES_COMPRESSION + - ICP_ACCEL_CAPABILITIES_SHA3_EXT + ICP_ACCEL_CAPABILITIES_SM2 + - ICP_ACCEL_CAPABILITIES_SM3 + ICP_ACCEL_CAPABILITIES_SM4 + - ICP_ACCEL_CAPABILITIES_CHACHA_POLY + - ICP_ACCEL_CAPABILITIES_AESGCM_SPC + - ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY64 + - ICP_ACCEL_CAPABILITIES_LZ4_COMPRESSION + - ICP_ACCEL_CAPABILITIES_LZ4S_COMPRESSION; + u32 capabilities_sym, capabilities_sym_cipher, capabilities_sym_auth, + capabilities_asym, capabilities_dc; /* Get fused capabilities */ vffusectl1 = pci_read_config(pdev, ADF_4XXXIOV_VFFUSECTL1_OFFSET, 4); - if (vffusectl1 & BIT(7)) { - capabilities &= - ~(ICP_ACCEL_CAPABILITIES_SM3 + ICP_ACCEL_CAPABILITIES_SM4); + capabilities_sym_cipher = ICP_ACCEL_CAPABILITIES_HKDF | + ICP_ACCEL_CAPABILITIES_SM4 | ICP_ACCEL_CAPABILITIES_CHACHA_POLY | + ICP_ACCEL_CAPABILITIES_AESGCM_SPC | ICP_ACCEL_CAPABILITIES_AES_V2; + capabilities_sym_auth = ICP_ACCEL_CAPABILITIES_SM3 | + ICP_ACCEL_CAPABILITIES_SHA3 | ICP_ACCEL_CAPABILITIES_SHA3_EXT; + + /* A set bit in vffusectl1 means the feature is OFF in this SKU */ + if (vffusectl1 & ICP_ACCEL_4XXXVF_MASK_CIPHER_SLICE) { + capabilities_sym_cipher &= ~ICP_ACCEL_CAPABILITIES_HKDF; + capabilities_sym_cipher &= ~ICP_ACCEL_CAPABILITIES_SM4; } - if (vffusectl1 & BIT(6)) { - capabilities &= ~ICP_ACCEL_CAPABILITIES_SM3; + + if (vffusectl1 & ICP_ACCEL_4XXXVF_MASK_UCS_SLICE) { + capabilities_sym_cipher &= ~ICP_ACCEL_CAPABILITIES_CHACHA_POLY; + capabilities_sym_cipher &= ~ICP_ACCEL_CAPABILITIES_AESGCM_SPC; + capabilities_sym_cipher &= ~ICP_ACCEL_CAPABILITIES_AES_V2; } - if (vffusectl1 & BIT(3)) { - capabilities &= ~(ICP_ACCEL_CAPABILITIES_COMPRESSION + - ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY64); + + if (vffusectl1 & ICP_ACCEL_4XXXVF_MASK_AUTH_SLICE) { + capabilities_sym_auth &= ~ICP_ACCEL_CAPABILITIES_SM3; + capabilities_sym_auth &= ~ICP_ACCEL_CAPABILITIES_SHA3; + capabilities_sym_auth &= ~ICP_ACCEL_CAPABILITIES_SHA3_EXT; } - if (vffusectl1 & BIT(2)) { - capabilities &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC; + + if (vffusectl1 & ICP_ACCEL_4XXXVF_MASK_SMX_SLICE) { + capabilities_sym_cipher &= ~ICP_ACCEL_CAPABILITIES_SM4; + capabilities_sym_auth &= ~ICP_ACCEL_CAPABILITIES_SM3; } - if (vffusectl1 & BIT(1)) { - capabilities &= ~ICP_ACCEL_CAPABILITIES_AUTHENTICATION; + + if (capabilities_sym_cipher) + capabilities_sym_cipher |= ICP_ACCEL_CAPABILITIES_CIPHER; + + if (capabilities_sym_auth) + capabilities_sym_auth |= ICP_ACCEL_CAPABILITIES_AUTHENTICATION; + + capabilities_sym = capabilities_sym_cipher | capabilities_sym_auth; + + if (capabilities_sym) + capabilities_sym |= ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC; + + capabilities_asym = ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC | + ICP_ACCEL_CAPABILITIES_SM2 | ICP_ACCEL_CAPABILITIES_ECEDMONT; + + if (vffusectl1 & ICP_ACCEL_4XXXVF_MASK_PKE_SLICE) { + capabilities_asym &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC; + capabilities_asym &= ~ICP_ACCEL_CAPABILITIES_SM2; + capabilities_asym &= ~ICP_ACCEL_CAPABILITIES_ECEDMONT; } - if (vffusectl1 & BIT(0)) { - capabilities &= ~ICP_ACCEL_CAPABILITIES_CIPHER; + + capabilities_dc = ICP_ACCEL_CAPABILITIES_COMPRESSION | + ICP_ACCEL_CAPABILITIES_LZ4_COMPRESSION | + ICP_ACCEL_CAPABILITIES_LZ4S_COMPRESSION | + ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY64; + + if (vffusectl1 & ICP_ACCEL_4XXXVF_MASK_COMPRESS_SLICE) { + capabilities_dc &= ~ICP_ACCEL_CAPABILITIES_COMPRESSION; + capabilities_dc &= ~ICP_ACCEL_CAPABILITIES_LZ4_COMPRESSION; + capabilities_dc &= ~ICP_ACCEL_CAPABILITIES_LZ4S_COMPRESSION; + capabilities_dc &= ~ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY64; } - return capabilities; + + return capabilities_sym | capabilities_dc | capabilities_asym; } static void diff --git a/sys/dev/qat/qat_hw/qat_4xxxvf/adf_4xxxvf_hw_data.h b/sys/dev/qat/qat_hw/qat_4xxxvf/adf_4xxxvf_hw_data.h index 83c034f543c9..a702fc69dde7 100644 --- a/sys/dev/qat/qat_hw/qat_4xxxvf/adf_4xxxvf_hw_data.h +++ b/sys/dev/qat/qat_hw/qat_4xxxvf/adf_4xxxvf_hw_data.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause */ -/* Copyright(c) 2007-2022 Intel Corporation */ +/* Copyright(c) 2007-2025 Intel Corporation */ #ifndef ADF_4XXXVF_HW_DATA_H_ #define ADF_4XXXVF_HW_DATA_H_ @@ -27,6 +27,18 @@ #define ADF_4XXXIOV_VFFUSECTL4_OFFSET (0x1C4) #define ADF_4XXXIOV_VFFUSECTL5_OFFSET (0x1C8) +/*qat_4xxxvf fuse bits are same as qat_4xxx*/ +enum icp_qat_4xxxvf_slice_mask { + ICP_ACCEL_4XXXVF_MASK_CIPHER_SLICE = 0x01, + ICP_ACCEL_4XXXVF_MASK_AUTH_SLICE = 0x02, + ICP_ACCEL_4XXXVF_MASK_PKE_SLICE = 0x04, + ICP_ACCEL_4XXXVF_MASK_COMPRESS_SLICE = 0x08, + ICP_ACCEL_4XXXVF_MASK_UCS_SLICE = 0x10, + ICP_ACCEL_4XXXVF_MASK_EIA3_SLICE = 0x20, + /*SM3&SM4 are indicated by same bit*/ + ICP_ACCEL_4XXXVF_MASK_SMX_SLICE = 0x80, +}; + void adf_init_hw_data_4xxxiov(struct adf_hw_device_data *hw_data); void adf_clean_hw_data_4xxxiov(struct adf_hw_device_data *hw_data); u32 adf_4xxxvf_get_hw_cap(struct adf_accel_dev *accel_dev);