From owner-freebsd-security@freebsd.org Fri Jan 5 18:44:49 2018 Return-Path: Delivered-To: freebsd-security@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 41FA2EB9597 for ; Fri, 5 Jan 2018 18:44:49 +0000 (UTC) (envelope-from eric@metricspace.net) Received: from mail.metricspace.net (mail.metricspace.net [IPv6:2001:470:1f11:617::107]) by mx1.freebsd.org (Postfix) with ESMTP id 1C4EE77A0A for ; Fri, 5 Jan 2018 18:44:49 +0000 (UTC) (envelope-from eric@metricspace.net) Received: from [192.168.43.57] (mobile-166-171-187-244.mycingular.net [166.171.187.244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (Client did not present a certificate) (Authenticated sender: eric) by mail.metricspace.net (Postfix) with ESMTPSA id 9B8548984 for ; Fri, 5 Jan 2018 18:44:46 +0000 (UTC) Subject: Re: Intel hardware bug To: freebsd-security@freebsd.org References: <736a2b77-d4a0-b03f-8a6b-6a717f5744d4@metricspace.net> <2594.1515141192@segfault.tristatelogic.com> <809675000.867372.1515146821354@mail.yahoo.com> <250f3a77-822b-fba5-dcd7-758dfec94554@metricspace.net> From: Eric McCorkle Message-ID: Date: Fri, 5 Jan 2018 13:44:46 -0500 User-Agent: Mozilla/5.0 (X11; FreeBSD amd64; rv:52.0) Gecko/20100101 Thunderbird/52.5.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-BeenThere: freebsd-security@freebsd.org X-Mailman-Version: 2.1.25 Precedence: list List-Id: "Security issues \[members-only posting\]" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 05 Jan 2018 18:44:49 -0000 On 01/05/2018 11:40, Nathan Whitehorn wrote: > POWER has the same thing. It's actually stronger separation, since user > processes don't share addresses either -- all processes, including the > kernel, have windowed access to an 80-bit address space, so no process > can even describe an address in another process's address space. There > are ways, of course, in which IBM could have messed up the > implementation, so the fact that it *should* be secure does not mean it > *is*. That's interesting, as it conflicts with Red Hat's vulnerability disclosure. It that because the silicon is buggy, or because Linux somehow ends up being vulnerable when it need not be? > > SPARC avoids the issue because almost all implementations are in-order. Definitely not true of the post-Oracle models. I saw a tech talk on the core once.