From owner-svn-src-all@FreeBSD.ORG Thu May 24 22:14:39 2012 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id C7E57106564A; Thu, 24 May 2012 22:14:39 +0000 (UTC) (envelope-from nwhitehorn@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id B2A348FC0C; Thu, 24 May 2012 22:14:39 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.4/8.14.4) with ESMTP id q4OMEd55063524; Thu, 24 May 2012 22:14:39 GMT (envelope-from nwhitehorn@svn.freebsd.org) Received: (from nwhitehorn@localhost) by svn.freebsd.org (8.14.4/8.14.4/Submit) id q4OMEdY2063522; Thu, 24 May 2012 22:14:39 GMT (envelope-from nwhitehorn@svn.freebsd.org) Message-Id: <201205242214.q4OMEdY2063522@svn.freebsd.org> From: Nathan Whitehorn Date: Thu, 24 May 2012 22:14:39 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r235943 - head/sys/powerpc/include X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 24 May 2012 22:14:39 -0000 Author: nwhitehorn Date: Thu May 24 22:14:39 2012 New Revision: 235943 URL: http://svn.freebsd.org/changeset/base/235943 Log: Atomic operation acquire barriers also need to be isync on 64-bit systems. Modified: head/sys/powerpc/include/atomic.h Modified: head/sys/powerpc/include/atomic.h ============================================================================== --- head/sys/powerpc/include/atomic.h Thu May 24 22:06:00 2012 (r235942) +++ head/sys/powerpc/include/atomic.h Thu May 24 22:14:39 2012 (r235943) @@ -52,7 +52,7 @@ #define rmb() __asm __volatile("lwsync" : : : "memory") #define wmb() __asm __volatile("lwsync" : : : "memory") #define __ATOMIC_REL() __asm __volatile("lwsync" : : : "memory") -#define __ATOMIC_ACQ() __asm __volatile("lwsync" : : : "memory") +#define __ATOMIC_ACQ() __asm __volatile("isync" : : : "memory") #else #define mb() __asm __volatile("sync" : : : "memory") #define rmb() __asm __volatile("sync" : : : "memory")