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Date:      Mon, 12 Jun 2023 13:50:25 GMT
From:      Mitchell Horne <mhorne@FreeBSD.org>
To:        src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-branches@FreeBSD.org
Subject:   git: 9834e0f2767a - stable/13 - riscv timer: use stimecmp CSR when available
Message-ID:  <202306121350.35CDoPhk089447@gitrepo.freebsd.org>

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The branch stable/13 has been updated by mhorne:

URL: https://cgit.FreeBSD.org/src/commit/?id=9834e0f2767a27d237e6820ecd67b24e65323ece

commit 9834e0f2767a27d237e6820ecd67b24e65323ece
Author:     Mitchell Horne <mhorne@FreeBSD.org>
AuthorDate: 2023-05-25 17:07:49 +0000
Commit:     Mitchell Horne <mhorne@FreeBSD.org>
CommitDate: 2023-06-12 13:49:55 +0000

    riscv timer: use stimecmp CSR when available
    
    The Sstc extension defines a new stimecmp CSR, allowing supervisor
    software to set the timer, rather than just read it. When supported,
    using this avoids the frequent trips through the SBI every time the
    CPU's timer expires.
    
    Reviewed by:    jhb
    MFC after:      2 weeks
    Sponsored by:   The FreeBSD Foundation
    Differential Revision:  https://reviews.freebsd.org/D40241
    
    (cherry picked from commit cadaabcc720bb20d6d604c4792acb29072d2882d)
---
 sys/riscv/riscv/timer.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/sys/riscv/riscv/timer.c b/sys/riscv/riscv/timer.c
index 9c333b42059e..1df8fb246309 100644
--- a/sys/riscv/riscv/timer.c
+++ b/sys/riscv/riscv/timer.c
@@ -53,6 +53,7 @@ __FBSDID("$FreeBSD$");
 
 #include <machine/cpufunc.h>
 #include <machine/intr.h>
+#include <machine/md_var.h>
 #include <machine/sbi.h>
 
 #include <dev/ofw/openfirm.h>
@@ -84,6 +85,16 @@ get_timecount(void)
 	return (rdtime());
 }
 
+static inline void
+set_timecmp(uint64_t timecmp)
+{
+
+	if (has_sstc)
+		csr_write(stimecmp, timecmp);
+	else
+		sbi_set_timer(timecmp);
+}
+
 static u_int
 riscv_timer_tc_get_timecount(struct timecounter *tc __unused)
 {
@@ -107,7 +118,7 @@ riscv_timer_et_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
 
 	if (first != 0) {
 		counts = ((uint32_t)et->et_frequency * first) >> 32;
-		sbi_set_timer(get_timecount() + counts);
+		set_timecmp(get_timecount() + counts);
 		csr_set(sie, SIE_STIE);
 
 		return (0);



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