From owner-freebsd-hackers@FreeBSD.ORG Thu Aug 5 15:59:40 2010 Return-Path: Delivered-To: freebsd-hackers@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 2E9FE1065679; Thu, 5 Aug 2010 15:59:40 +0000 (UTC) (envelope-from mdf356@gmail.com) Received: from mail-gy0-f182.google.com (mail-gy0-f182.google.com [209.85.160.182]) by mx1.freebsd.org (Postfix) with ESMTP id C5BF88FC1A; Thu, 5 Aug 2010 15:59:39 +0000 (UTC) Received: by gyg4 with SMTP id 4so3183035gyg.13 for ; Thu, 05 Aug 2010 08:59:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:sender:received :in-reply-to:references:date:x-google-sender-auth:message-id:subject :from:to:cc:content-type:content-transfer-encoding; bh=qujKzgS1L1L6tNSHytuGoNPYa9NOONgGyJ3SSGqHt6E=; b=H7Pwe4QKvnKdJcAO4mIkDzJtP53RE4sP9IaFYxs48LqEjKmwY4zospvG7jld58DI+e Xo7A1MgWkMEPlhTui/74vgl6FWZwO4h2k+xlMe2YFNzF/Syqu8j1t1cbxpAXlMcCFU7s ysWRlaGp56NGTquo6zZqijTqOmkd94ZZS/db0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type :content-transfer-encoding; b=KbHnXNRa9xEhSSqK0ebxFl0UCS3vd+zQqeKaHfQLVw+1SjpKVzPJbojYWNLZ10KZLr WNpd/81xnbNfCZYdJA9kQYoAk8o30pre06EvOX15OZvfNXnQ/i1M/O9chDV92raOB5S5 H1iBdjj8L3/V6l7aijo16zTvSd9arA9xBCBio= MIME-Version: 1.0 Received: by 10.150.69.20 with SMTP id r20mr12345124yba.304.1281023977437; Thu, 05 Aug 2010 08:59:37 -0700 (PDT) Sender: mdf356@gmail.com Received: by 10.42.3.140 with HTTP; Thu, 5 Aug 2010 08:59:37 -0700 (PDT) In-Reply-To: <201008041455.26066.jhb@freebsd.org> References: <201008041026.17553.jhb@freebsd.org> <201008041455.26066.jhb@freebsd.org> Date: Thu, 5 Aug 2010 08:59:37 -0700 X-Google-Sender-Auth: kKXescuvGqjCHgcg21ILPweaFYI Message-ID: From: mdf@FreeBSD.org To: John Baldwin Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable Cc: freebsd-hackers@freebsd.org Subject: Re: sched_pin() versus PCPU_GET X-BeenThere: freebsd-hackers@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Technical Discussions relating to FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Aug 2010 15:59:40 -0000 On Wed, Aug 4, 2010 at 11:55 AM, John Baldwin wrote: > On Wednesday, August 04, 2010 12:20:31 pm mdf@freebsd.org wrote: >> On Wed, Aug 4, 2010 at 2:26 PM, John Baldwin wrote: >> > On Tuesday, August 03, 2010 9:46:16 pm mdf@freebsd.org wrote: >> >> On Fri, Jul 30, 2010 at 2:31 PM, John Baldwin wrote= : >> >> > On Friday, July 30, 2010 10:08:22 am John Baldwin wrote: >> >> >> On Thursday, July 29, 2010 7:39:02 pm mdf@freebsd.org wrote: >> >> >> > We've seen a few instances at work where witness_warn() in ast() >> >> >> > indicates the sched lock is still held, but the place it claims = it was >> >> >> > held by is in fact sometimes not possible to keep the lock, like= : >> >> >> > >> >> >> > =A0 =A0 thread_lock(td); >> >> >> > =A0 =A0 td->td_flags &=3D ~TDF_SELECT; >> >> >> > =A0 =A0 thread_unlock(td); >> >> >> > >> >> >> > What I was wondering is, even though the assembly I see in objdu= mp -S >> >> >> > for witness_warn has the increment of td_pinned before the PCPU_= GET: >> >> >> > >> >> >> > ffffffff802db210: =A0 65 48 8b 1c 25 00 00 =A0 =A0mov =A0 =A0%gs= :0x0,%rbx >> >> >> > ffffffff802db217: =A0 00 00 >> >> >> > ffffffff802db219: =A0 ff 83 04 01 00 00 =A0 =A0 =A0 incl =A0 0x1= 04(%rbx) >> >> >> > =A0 =A0 =A0* Pin the thread in order to avoid problems with thre= ad migration. >> >> >> > =A0 =A0 =A0* Once that all verifies are passed about spinlocks o= wnership, >> >> >> > =A0 =A0 =A0* the thread is in a safe path and it can be unpinned= . >> >> >> > =A0 =A0 =A0*/ >> >> >> > =A0 =A0 sched_pin(); >> >> >> > =A0 =A0 lock_list =3D PCPU_GET(spinlocks); >> >> >> > ffffffff802db21f: =A0 65 48 8b 04 25 48 00 =A0 =A0mov =A0 =A0%gs= :0x48,%rax >> >> >> > ffffffff802db226: =A0 00 00 >> >> >> > =A0 =A0 if (lock_list !=3D NULL && lock_list->ll_count !=3D 0) { >> >> >> > ffffffff802db228: =A0 48 85 c0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0te= st =A0 %rax,%rax >> >> >> > =A0 =A0 =A0* Pin the thread in order to avoid problems with thre= ad migration. >> >> >> > =A0 =A0 =A0* Once that all verifies are passed about spinlocks o= wnership, >> >> >> > =A0 =A0 =A0* the thread is in a safe path and it can be unpinned= . >> >> >> > =A0 =A0 =A0*/ >> >> >> > =A0 =A0 sched_pin(); >> >> >> > =A0 =A0 lock_list =3D PCPU_GET(spinlocks); >> >> >> > ffffffff802db22b: =A0 48 89 85 f0 fe ff ff =A0 =A0mov =A0 =A0%ra= x,-0x110(%rbp) >> >> >> > ffffffff802db232: =A0 48 89 85 f8 fe ff ff =A0 =A0mov =A0 =A0%ra= x,-0x108(%rbp) >> >> >> > =A0 =A0 if (lock_list !=3D NULL && lock_list->ll_count !=3D 0) { >> >> >> > ffffffff802db239: =A0 0f 84 ff 00 00 00 =A0 =A0 =A0 je =A0 =A0 f= fffffff802db33e >> >> >> > >> >> >> > ffffffff802db23f: =A0 44 8b 60 50 =A0 =A0 =A0 =A0 =A0 =A0 mov = =A0 =A00x50(%rax),%r12d >> >> >> > >> >> >> > is it possible for the hardware to do any re-ordering here? >> >> >> > >> >> >> > The reason I'm suspicious is not just that the code doesn't have= a >> >> >> > lock leak at the indicated point, but in one instance I can see = in the >> >> >> > dump that the lock_list local from witness_warn is from the pcpu >> >> >> > structure for CPU 0 (and I was warned about sched lock 0), but t= he >> >> >> > thread id in panic_cpu is 2. =A0So clearly the thread was being = migrated >> >> >> > right around panic time. >> >> >> > >> >> >> > This is the amd64 kernel on stable/7. =A0I'm not sure exactly wh= at kind >> >> >> > of hardware; it's a 4-way Intel chip from about 3 or 4 years ago= IIRC. >> >> >> > >> >> >> > So... do we need some kind of barrier in the code for sched_pin(= ) for >> >> >> > it to really do what it claims? =A0Could the hardware have re-or= dered >> >> >> > the "mov =A0 =A0%gs:0x48,%rax" PCPU_GET to before the sched_pin(= ) >> >> >> > increment? >> >> >> >> >> >> Hmmm, I think it might be able to because they refer to different = locations. >> >> >> >> >> >> Note this rule in section 8.2.2 of Volume 3A: >> >> >> >> >> >> =A0 =95 Reads may be reordered with older writes to different loca= tions but not >> >> >> =A0 =A0 with older writes to the same location. >> >> >> >> >> >> It is certainly true that sparc64 could reorder with RMO. =A0I bel= ieve ia64 >> >> >> could reorder as well. =A0Since sched_pin/unpin are frequently use= d to provide >> >> >> this sort of synchronization, we could use memory barriers in pin/= unpin >> >> >> like so: >> >> >> >> >> >> sched_pin() >> >> >> { >> >> >> =A0 =A0 =A0 td->td_pinned =3D atomic_load_acq_int(&td->td_pinned) = + 1; >> >> >> } >> >> >> >> >> >> sched_unpin() >> >> >> { >> >> >> =A0 =A0 =A0 atomic_store_rel_int(&td->td_pinned, td->td_pinned - 1= ); >> >> >> } >> >> >> >> >> >> We could also just use atomic_add_acq_int() and atomic_sub_rel_int= (), but they >> >> >> are slightly more heavyweight, though it would be more clear what = is happening >> >> >> I think. >> >> > >> >> > However, to actually get a race you'd have to have an interrupt fir= e and >> >> > migrate you so that the speculative read was from the other CPU. = =A0However, I >> >> > don't think the speculative read would be preserved in that case. = =A0The CPU >> >> > has to return to a specific PC when it returns from the interrupt a= nd it has >> >> > no way of storing the state for what speculative reordering it migh= t be >> >> > doing, so presumably it is thrown away? =A0I suppose it is possible= that it >> >> > actually retires both instructions (but reordered) and then returns= to the PC >> >> > value after the read of listlocks after the interrupt. =A0However, = in that case >> >> > the scheduler would not migrate as it would see td_pinned !=3D 0. = =A0To get the >> >> > race you have to have the interrupt take effect prior to modifying = td_pinned, >> >> > so I think the processor would have to discard the reordered read o= f >> >> > listlocks so it could safely resume execution at the 'incl' instruc= tion. >> >> > >> >> > The other nit there on x86 at least is that the incl instruction is= doing >> >> > both a read and a write and another rule in the section 8.2.2 is th= is: >> >> > >> >> > =A0=95 Reads are not reordered with other reads. >> >> > >> >> > That would seem to prevent the read of listlocks from passing the r= ead of >> >> > td_pinned in the incl instruction on x86. >> >> >> >> I wonder how that's interpreted in the microcode, though? =A0I.e. if = the >> >> incr instruction decodes to load, add, store, does the h/w allow the >> >> later reads to pass the final store? >> > >> > Well, the architecture is defined in terms of the ISA, not the microco= de, per >> > se, so I think it would have to treat the read for the incl as being a= n earlier >> > read than 'spinlocks'. >> > >> >> I added the following: >> >> >> >> =A0 =A0 =A0 sched_pin(); >> >> =A0 =A0 =A0 lock_list =3D PCPU_GET(spinlocks); >> >> =A0 =A0 =A0 if (lock_list !=3D NULL && lock_list->ll_count !=3D 0) { >> >> + =A0 =A0 =A0 =A0 =A0 =A0 /* XXX debug for bug 67957 */ >> >> + =A0 =A0 =A0 =A0 =A0 =A0 mfence(); >> >> + =A0 =A0 =A0 =A0 =A0 =A0 lle =3D PCPU_GET(spinlocks); >> >> + =A0 =A0 =A0 =A0 =A0 =A0 if (lle !=3D lock_list) { >> >> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 panic("Bug 67957: had lock = list %p, now %p\n", >> >> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 lock_list, lle); >> >> + =A0 =A0 =A0 =A0 =A0 =A0 } >> >> + =A0 =A0 =A0 =A0 =A0 =A0 /* XXX end debug */ >> >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 sched_unpin(); >> >> >> >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 /* >> >> >> >> ... and the panic triggered. =A0I think it's more likely that some >> >> barrier is needed in sched_pin() than that %gs is getting corrupted >> >> but can always be dereferenced. >> > >> > Actually, I would beg to differ in that case. =A0If PCPU_GET(spinlocks= ) >> > returns non-NULL, then it means that you hold a spin lock, >> >> ll_count is 0 for the "correct" pc_spinlocks and non-zero for the >> "wrong" one, though. =A0So I think it can be non-NULL but the current >> thread/CPU doesn't hold a spinlock. > > Hmm, does the 'lock_list' pointer value in the dump match 'lock_list' > from another CPU? Yes: (gdb) p panic_cpu $9 =3D 2 (gdb) p dumptid $12 =3D 100751 (gdb) p cpuhead.slh_first->pc_allcpu.sle_next->pc_curthread->td_tid $14 =3D 100751 (gdb) p *cpuhead.slh_first->pc_allcpu.sle_next $6 =3D { pc_curthread =3D 0xffffff00716d6960, pc_cpuid =3D 2, pc_spinlocks =3D 0xffffffff80803198, (gdb) p lock_list $2 =3D (struct lock_list_entry *) 0xffffffff80803fb0 (gdb) p *cpuhead.slh_first->pc_allcpu.sle_next->pc_allcpu.sle_next->pc_allc= pu.sle_next $8 =3D { pc_curthread =3D 0xffffff0005479960, pc_cpuid =3D 0, pc_spinlocks =3D 0xffffffff80803fb0, I.e. we're dumping on CPU 2, but the lock_list pointer that was saved in the dump matches that of CPU 0. Thanks, matthew