Date: Thu, 19 Jan 2017 13:45:25 -0800 From: Thomas Skibo <thomasskibo@yahoo.com> To: Warner Losh <imp@bsdimp.com> Cc: Kurt Jaeger <pi@opsec.eu>, "freebsd-arm@freebsd.org" <freebsd-arm@freebsd.org> Subject: Re: u-boot ports for Zedboard and Zybo Message-ID: <CFB0B302-E146-48F5-8EF9-4B23928AA059@yahoo.com> In-Reply-To: <CANCZdfrfurQaQXviNJ4Q=FwVgtFGuBEqQgOLtV5HuVzOT=fRMg@mail.gmail.com> References: <640059E8-B9DD-4289-BA59-2E02A4D91F87@yahoo.com> <20170116173329.GH13006@home.opsec.eu> <B648E0C0-4DE4-4809-8FEC-FE9735DC178A@yahoo.com> <CANCZdfrfurQaQXviNJ4Q=FwVgtFGuBEqQgOLtV5HuVzOT=fRMg@mail.gmail.com>
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> On Jan 16, 2017, at 10:20 AM, Warner Losh <imp@bsdimp.com> wrote: >=20 > Any chance you could rebase this onto the new u-boot-master framework? > Or are the changes not yet merged back into u-boot upstream? >=20 > Warner >=20 >=20 I was able to fix the API compile issue but what is missing is a feature = I really want which is u-boot automatically loading the PL (FPGA fabric) = from =E2=80=9Cfpga.bin=E2=80=9D. I=E2=80=99ve been working on a video = driver which can only work if the PL/FPGA design is loaded before the = kernel is booted. I tried to enable this feature in both your u-boot = tree and the official repository and it fails to link the spl stage in = both cases. I=E2=80=99d like to submit these ports as I have them, based upon = Xilinx=E2=80=99s u-boot tree at github.com/Xilinx/u-boot-xlnx. It works = great with only a simple patch. I=E2=80=99d submit them via the bug = system as described in the porter=E2=80=99s handbook. What do you think? =E2=80=94Thomas
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