From owner-p4-projects@FreeBSD.ORG Sun May 20 03:40:06 2012 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id 4176A1065688; Sun, 20 May 2012 03:40:06 +0000 (UTC) Delivered-To: perforce@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id D909F1065680 for ; Sun, 20 May 2012 03:40:05 +0000 (UTC) (envelope-from bb+lists.freebsd.perforce@cyrus.watson.org) Received: from skunkworks.freebsd.org (skunkworks.freebsd.org [IPv6:2001:4f8:fff6::2d]) by mx1.freebsd.org (Postfix) with ESMTP id BEC558FC17 for ; Sun, 20 May 2012 03:40:05 +0000 (UTC) Received: from skunkworks.freebsd.org (localhost [127.0.0.1]) by skunkworks.freebsd.org (8.14.4/8.14.4) with ESMTP id q4K3e5v9032785 for ; Sun, 20 May 2012 03:40:05 GMT (envelope-from bb+lists.freebsd.perforce@cyrus.watson.org) Received: (from perforce@localhost) by skunkworks.freebsd.org (8.14.4/8.14.4/Submit) id q4K3e5tF032782 for perforce@freebsd.org; Sun, 20 May 2012 03:40:05 GMT (envelope-from bb+lists.freebsd.perforce@cyrus.watson.org) Date: Sun, 20 May 2012 03:40:05 GMT Message-Id: <201205200340.q4K3e5tF032782@skunkworks.freebsd.org> X-Authentication-Warning: skunkworks.freebsd.org: perforce set sender to bb+lists.freebsd.perforce@cyrus.watson.org using -f From: Robert Watson To: Perforce Change Reviews Precedence: bulk Cc: Subject: PERFORCE change 211410 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.5 List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 20 May 2012 03:40:06 -0000 http://p4web.freebsd.org/@@211410?ac=10 Change 211410 by rwatson@rwatson_svr_ctsrd_mipsbuild on 2012/05/20 03:39:27 Start adapting cp2.h for use in FreeBSD: - Improved header guards. - Adjust aspects of ABI and hardware capability register allocation that remain "in flight": trim not immediately relevant registers, add new kernel temporary registers. - Remove a lot of nops that are believed no longer required due to lots of work on the CHERI pipeline. Affected files ... .. //depot/projects/ctsrd/cheribsd/src/sys/mips/cheri/cp2.h#2 edit Differences ... ==== //depot/projects/ctsrd/cheribsd/src/sys/mips/cheri/cp2.h#2 (text+ko) ==== @@ -28,10 +28,8 @@ * SUCH DAMAGE. */ -#ifndef _CHERIDEMO_CP2_H_ -#define _CHERIDEMO_CP2_H_ - -#include "include/mips.h" +#ifndef _MIPS_CHERI_CP2_H_ +#define _MIPS_CHERI_CP2_H_ /* * CHERI ISA-defined constants for capabilities. @@ -70,23 +68,10 @@ /* * A blend of hardware and software allocation of capability registers. - * Deimos ABI/KBI conventions marked with a '+'. */ -#define CHERI_CR_C0 0 /* MIPS load/store capability. */ - -#define CHERI_CR_CV0 1 /* + Return capability 0. */ -#define CHERI_CR_CV1 2 /* + Return capability 1. */ -#define CHERI_CR_CA0 3 /* + Argument capability 0. */ -#define CHERI_CR_CA1 4 /* + Argument capability 1. */ -#define CHERI_CR_CA2 5 /* + Argument capability 2. */ -#define CHERI_CR_CA3 6 /* + Argument capability 3. */ -#define CHERI_CR_CT0 7 /* + Temporary capability 0. */ - -#define CHERI_CR_TS 24 /* + Capability to touchscreen coordinates. */ -#define CHERI_CR_FB 25 /* + Capability to video frame buffer. */ - -#define CHERI_CR_RCC 26 /* RCC: return code capability. */ -#define CHERI_CR_IDC 27 /* IDC: invoked data capability. */ +#define CHERI_CR_C0 0 /* MIPS fetch/load/store capability. */ +#define CHERI_CR_KT0 26 /* KT0: temporary kernel capability. */ +#define CHERI_CR_KT1 27 /* KT1: temporary kernel capability. */ #define CHERI_CR_TSC 28 /* TSC: trusted stack capability. */ #define CHERI_CR_KCC 29 /* KCC: kernel code capability. */ #define CHERI_CR_KDC 30 /* KDC: kernel data capability. */ @@ -120,16 +105,9 @@ * the CHERI ISA spec. v1.4 is expected to renumber the specific * purpose capabilities to be at the bottom, rather than the top, of * the capability register space (per Ross Anderson's suggestion). - * - * Capability registers allocated as part of the ABI. */ - struct capability cf_cv0, cf_cv1; - struct capability cf_ca0, cf_ca1, cf_ca2, cf_ca3; - struct capability cf_ct0; - - /* - * Capability registers not yet allocated as part of the ABI. - */ + struct capability cf_c1, cf_c2, cf_c3, cf_c4; + struct capability cf_c5, cf_c6, cf_c7; struct capability cf_c8, cf_c9, cf_c10, cf_c11, cf_c12; struct capability cf_c13, cf_c14, cf_c15, cf_c16, cf_c17; struct capability cf_c18, cf_c19, cf_c20, cf_c21, cf_c22; @@ -137,9 +115,9 @@ /* * Special-purpose capability registers that must be preserved on a - * user context switch. Note that KCC and KDC are omitted. + * user context switch. Note that KT0, KT1, KCC, and KDC are omitted. */ - struct capability cf_rcc, cf_idc, cf_tsc; + struct capability cf_tsc; /* Program counter capability. */ struct capability cf_pcc; @@ -147,31 +125,22 @@ /* * CP2 capability register manipulation macros. - * - * XXXRW: lots of nops due to non-forwarding of loads/stores and capability - * instructions. */ #define CP2_CR_GET_BASE(crn, v) do { \ __asm__ __volatile__ ( \ - "nop; nop; nop; nop; " \ "cgetbase %0, $c%1; " \ - "nop; nop; nop; nop" : \ "=r" (v) : "i" (crn)); \ } while (0) #define CP2_CR_GET_UPERMS(crn, v) do { \ __asm__ __volatile__ ( \ - "nop; nop; nop; nop; " \ "cgetperms %0, $c%1; " \ - "nop; nop; nop; nop" : \ "=r" (v) : "i" (crn)); \ } while (0) #define CP2_CR_GET_OTYPE(crn, v) do { \ __asm__ __volatile__ ( \ - "nop; nop; nop; nop; " \ "cgettype %0, $c%1; " \ - "nop; nop; nop; nop" : \ "=r" (v) : "i" (crn)); \ } while (0) @@ -179,17 +148,13 @@ #define CP2_CR_GET_LENGTH(crn, v) do { \ __asm__ __volatile__ ( \ - "nop; nop; nop; nop; " \ "cgetleng %0, $c%1; " \ - "nop; nop; nop; nop" : \ "=r" (v) : "i" (crn)); \ } while (0) #define CP2_CR_STORE(crn_from, crn_base, offset) do { \ __asm__ __volatile__ ( \ - "nop; nop; nop; nop; " \ "cscr $c%0, $c%1, %2; " \ - "nop; nop; nop; nop " : \ : "i" (crn_from), "i" (crn_base), "r" (offset)); \ } while (0) @@ -216,93 +181,71 @@ * closely. */ #define CP2_CR_MOVE(crn_to, crn_from) do { \ - __asm__ __volatile__ ("nop; nop; nop; nop"); \ if ((crn_to) == 0) \ __asm__ __volatile__ ("cmove $c%0, $c%1" : \ : "i" (crn_to), "i" (crn_from) : "memory"); \ else \ __asm__ __volatile__ ("cmove $c%0, $c%1" : \ : "i" (crn_to), "i" (crn_from)); \ - __asm__ __volatile__ ("nop; nop; nop; nop"); \ } while (0) #define CP2_CR_INC_BASE(crn_to, crn_from, v) do { \ if ((crn_to) == 0) \ __asm__ __volatile__ ( \ - "nop; nop; nop; nop; " \ "cincbase $c%0, $c%1, %2; " \ - "nop; nop; nop; nop" : \ : "i" (crn_to), "i" (crn_from), "r" (v) : \ "memory"); \ else \ __asm__ __volatile__ ( \ - "nop; nop; nop; nop; " \ "cincbase $c%0, $c%1, %2; " \ - "nop; nop; nop; nop" : \ : "i" (crn_to), "i" (crn_from), "r" (v)); \ } while (0) #define CP2_CR_AND_UPERMS(crn_to, crn_from, v) do { \ if ((crn_to) == 0) \ __asm__ __volatile__ ( \ - "nop; nop; nop; nop; " \ "candperm $c%0, $c%1, %2; " \ - "nop; nop; nop; nop" : \ : "i" (crn_to), "i" (crn_from), "r" (v) : \ "memory"); \ else \ __asm__ __volatile__ ( \ - "nop; nop; nop; nop; " \ "candperm $c%0, $c%1, %2; " \ - "nop; nop; nop; nop" : \ : "i" (crn_to), "i" (crn_from), "r" (v)); \ } while (0) #define CP2_CR_SET_OTYPE(crn_to, crn_from, v) do { \ if ((crn_to) == 0) \ __asm__ __volatile__ ( \ - "nop; nop; nop; nop; " \ "csettype $c%0, $c%1, %2; " \ - "nop; nop; nop; nop" : \ : "i" (crn_to), "i" (crn_from), "r" (v) : \ "memory"); \ else \ __asm__ __volatile__ ( \ - "nop; nop; nop; nop; " \ "csettype $c%0, $c%1, %2; " \ - "nop; nop; nop; nop" : \ : "i" (crn_to), "i" (crn_from), "r" (v)); \ } while (0) #define CP2_CR_SET_LENGTH(crn_to, crn_from, v) do { \ if ((crn_to) == 0) \ __asm__ __volatile__ ( \ - "nop; nop; nop; nop; " \ "cdecleng $c%0, $c%1, %2; " \ - "nop; nop; nop; nop" : \ : "i" (crn_to), "i" (crn_from), "r" (v) : \ "memory"); \ else \ __asm__ __volatile__ ( \ - "nop; nop; nop; nop; " \ "cdecleng $c%0, $c%1, %2; " \ - "nop; nop; nop; nop" : \ : "i" (crn_to), "i" (crn_from), "r" (v)); \ } while (0) #define CP2_CR_LOAD(crn_to, crn_base, offset) do { \ if ((crn_to) == 0) \ __asm__ __volatile__ ( \ - "nop; nop; nop; nop; " \ "clcr $c%0, $c%1, %2; " \ - "nop; nop; nop; nop" : \ : "i" (crn_to), "i" (crn_base), "r" (offset) : \ "memory"); \ else \ __asm__ __volatile__ ( \ - "nop; nop; nop; nop; " \ "clcr $c%0, $c%1, %2; " \ - "nop; nop; nop; nop" : \ : "i" (crn_to), "i" (crn_base), "r" (offset)); \ } while (0) @@ -340,65 +283,49 @@ */ #define CP2_LOAD_BYTE_VIA(crn, offset, b) do { \ __asm__ __volatile__ ( \ - "nop; nop; nop; nop; " \ "clbr %0, $c%1, %2; " \ - "nop; nop; nop; nop" : \ "=r" (b) : "i" (crn), "r" (offset) : "memory"); \ } while (0) #define CP2_LOAD_HWORD_VIA(crn, offset, h) do { \ __asm__ __volatile__ ( \ - "nop; nop; nop; nop; " \ "clhr %0, $c%1, %2; " \ - "nop; nop; nop; nop" : \ "=r" (b) : "i" (crn), "r" (offset) : "memory"); \ } while (0) #define CP2_LOAD_WORD_VIA(crn, offset, w) do { \ __asm__ __volatile__ ( \ - "nop; nop; nop; nop; " \ "clwr %0, $c%1, %2; " \ - "nop; nop; nop; nop" : \ "=r" (w) : "i" (crn), "r" (offset) : "memory"); \ } while (0) #define CP2_LOAD_DWORD_VIA(crn, offset, d) do { \ __asm__ __volatile__ ( \ - "nop; nop; nop; nop; " \ "cldr %0, $c%1, %2; " \ - "nop; nop; nop; nop" : \ "=r" (d) : "i" (crn), "r" (offset) : "memory"); \ } while (0) #define CP2_STORE_BYTE_VIA(crn, offset, b) do { \ __asm__ __volatile__ ( \ - "nop; nop; nop; nop; " \ "csbr %0, $c%1, %2; " \ - "nop; nop; nop; nop" : \ : "r" (b), "i" (crn), "r" (offset) : "memory"); \ } while (0) #define CP2_STORE_HWORD_VIA(crn, offset, h) do { \ __asm__ __volatile__ ( \ - "nop; nop; nop; nop; " \ "cshr %0, $c%1, %2; " \ - "nop; nop; nop; nop" : \ : "r" (h), "i" (crn), "r" (offset) : "memory"); \ } while (0) #define CP2_STORE_WORD_VIA(crn, offset, w) do { \ __asm__ __volatile__ ( \ - "nop; nop; nop; nop; " \ "cswr %0, $c%1, %2; " \ - "nop; nop; nop; nop" : \ : "r" (w), "i" (crn), "r" (offset) : "memory"); \ } while (0) #define CP2_STORE_DWORD_VIA(crn, offset, d) do { \ __asm__ __volatile__ ( \ - "nop; nop; nop; nop; " \ "csdr %0, $c%1, %2; " \ - "nop; nop; nop; nop" : \ : "r" (d), "i" (crn), "r" (offset) : "memory"); \ } while (0) @@ -425,4 +352,4 @@ void cp2_context_copy(struct cp2_frame *cf_destp, struct cp2_frame *cf_srcp); -#endif /* _CHERIDEMO_CP2_H_ */ +#endif /* _MIPS_CHERI_CP2_H_ */