Date: Wed, 15 Apr 2020 16:13:42 +0200 From: Heitai <heitai@minix-c11.org> To: freebsd-hackers@freebsd.org Subject: Re: try to Compile dev/drm2 with stable svn in hard under the kernel Message-ID: <20200415161342.0d38f18f@Dell-Station.lan> In-Reply-To: <20200414160026.5eb905df@Dell-Station.lan> References: <20200414160026.5eb905df@Dell-Station.lan>
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Konichiha, Hi, Ola, After investigation, thanks to DrMax and Segfault without them i can't find why... And i can try under my bad way for long time ; https://svnweb.freebsd.org/base/head/?view=3Dlog&pathrev=3D338285 But, I have an chiffred disk and the firmware maybe can't load at boot time. May be need to add this firmware to the /boot/modules but I don't know if it's the good way. I'd like just have the full resolution in the boot loader and the KERNEL boot for my work machine... Please say me were the best way about my ask. BRs, Heitai. Le Tue, 14 Apr 2020 16:00:26 +0200, Heitai <heitai@minix-c11.org> a =C3=A9crit : > Hello, >=20 > I try to compile with the stable kernel svn source code the drm2 > driver for have the correct and hightest resolution for my intel > video card at the boot time. >=20 > Sorry for the long log, I prefer paste all I have. > I hope I'm on the correct ML and if that isn't please say me how post. >=20 > I would like have same in the loader boot prompt. >=20 > Best Regard, > See after for better reading, > Heitai > -- >=20 > [___]--> my trying to debug the sys/dev/iicbus/iicbus_if.m=20 > by iicbus_if.h >=20 > [=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D] > /* > * Copyright (c) 1998 Nicolas Souchu > * All rights reserved. > * > * Redistribution and use in source and binary forms, with or without > * modification, are permitted provided that the following conditions > * are met: > * 1. Redistributions of source code must retain the above copyright > * notice, this list of conditions and the following disclaimer. > * 2. Redistributions in binary form must reproduce the above copyright > * notice, this list of conditions and the following disclaimer in > the > * documentation and/or other materials provided with the > distribution. * > * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' > AND > * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, > THE > * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR > PURPOSE > * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE > LIABLE > * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR > CONSEQUENTIAL > * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE > GOODS > * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS > INTERRUPTION) > * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, > STRICT > * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN > ANY WAY > * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY > OF > * SUCH DAMAGE. > * > * $FreeBSD: stable/12/sys/dev/iicbus/iicbus_if.m 323474 2017-09-11 > 23:47:49Z ian $ */ >=20 > #include <sys/bus.h> > #include <dev/iicbus/iic.h> >=20 > INTERFACE iicbus(void) >=20 > CODE { > struct iicbus_nosupport > { > return (ENODEV); > } ; >=20 > struct u_int, > iicbus_default_frequency(device_t bus, u_char speed) > { > return (100000); > } ; > } >=20 > /* > * Interpret interrupt > */ > struct intr { > device_t dev; > int event; > char *buf; > } ; >=20 > /* > * iicbus callback > * Request ownership of bus > * index: IIC_REQUEST_BUS or IIC_RELEASE_BUS > * data: pointer to int containing IIC_WAIT or IIC_DONTWAIT and either > IIC_INTR or IIC_NOINTR > * This function is allowed to sleep if *data contains IIC_WAIT. > */ > struct callback { > device_t dev; > int index; > caddr_t data; > } ;=20 >=20 > /* > * Send REPEATED_START condition > */ > struct repeated_start { > device_t dev; > u_char slave; > int timeout; > } iicbus_nosupport ; >=20 > /*) > * Send START condition > */ > struct start { > device_t dev; > u_char slave; > int timeout; > } iicbus_nosupport ; >=20 > /* > * Send STOP condition > */ > struct stop { > device_t dev; > } iicbus_nosupport ; >=20 > /* > * Read from I2C bus > */ > struct read { > device_t dev; > char *buf; > int len; > int *bytes; > int last; > int delay; > } iicbus_nosupport ; >=20 > /* > * Write to the I2C bus > */ > struct write { > device_t dev; > const char *buf; > int len; > int *bytes; > int timeout; > } iicbus_nosupport ; >=20 > /* > * Reset I2C bus > */ > struct reset { > device_t dev; > u_char speed; > u_char addr; > u_char *oldaddr; > } ; >=20 > /* > * Generalized Read/Write interface > */ > struct transfer { > device_t dev; > struct iic_msg *msgs; > uint32_t nmsgs; > } ; >=20 > /* > * Return the frequency in Hz for the bus running at the given=20 > * symbolic speed. Only the IIC_SLOW speed has meaning, it is always > * 100KHz. The UNKNOWN, FAST, and FASTEST rates all map to the > * configured bus frequency, or 100KHz when not otherwise configured. > */ > struct u_int, get_frequency { > device_t dev; > u_char speed; > } iicbus_default_frequency ; > [=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D] >=20 > [___]--> The # make buildkernel ERROR >=20 > [%=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D%] > make[1]: "/usr/src/Makefile.inc1" line 344: SYSTEM_COMPILER: libclang > will be built for bootstrapping a cross-compiler. make[1]: > "/usr/src/Makefile.inc1" line 349: SYSTEM_LINKER: libclang will be > built for bootstrapping a cross-linker. In file included from > /usr/src/sys/dev/drm2/drm_dp_iic_helper.c:31: > /usr/src/sys/dev/iicbus/iicbus_if.h:32:1: error: unknown type name > 'INTERFACE' INTERFACE iicbus(void) ^ > /usr/src/sys/dev/iicbus/iicbus_if.h:34:1: error: expected function > body after function declarator CODE { ^ > /usr/src/sys/dev/iicbus/iicbus_if.h:85:6: error: redefinition of > 'iicbus_nosupport' with a different type: 'struct start' vs 'struct > repeated_start' } iicbus_nosupport ; > ^ > /usr/src/sys/dev/iicbus/iicbus_if.h:76:6: note: previous definition is > here } iicbus_nosupport ; > ^ > /usr/src/sys/dev/iicbus/iicbus_if.h:92:3: error: redefinition of > 'iicbus_nosupport' with a different type: 'struct stop' vs 'struct > repeated_start' } iicbus_nosupport ; > ^ > /usr/src/sys/dev/iicbus/iicbus_if.h:76:6: note: previous definition is > here } iicbus_nosupport ; > ^ > /usr/src/sys/dev/iicbus/iicbus_if.h:104:6: error: redefinition of > 'iicbus_nosupport' with a different type: 'struct read' vs 'struct > repeated_start' } iicbus_nosupport ; > ^ > /usr/src/sys/dev/iicbus/iicbus_if.h:76:6: note: previous definition is > here } iicbus_nosupport ; > ^ > /usr/src/sys/dev/iicbus/iicbus_if.h:115:6: error: redefinition of > 'iicbus_nosupport' with a different type: 'struct write' vs 'struct > repeated_start' } iicbus_nosupport ; > ^ > /usr/src/sys/dev/iicbus/iicbus_if.h:76:6: note: previous definition is > here } iicbus_nosupport ; > ^ > /usr/src/sys/dev/iicbus/iicbus_if.h:142:13: error: expected identifier > or '(' struct u_int, get_frequency { > ^ > /usr/src/sys/dev/iicbus/iicbus_if.h:145:6: error: type specifier > missing, defaults to 'int' [-Werror,-Wimplicit-int] > } iicbus_default_frequency ; > ^ > /usr/src/sys/dev/drm2/drm_dp_iic_helper.c:268:2: error: use of > undeclared identifier 'iicbus_reset_desc' DEVMETHOD(iicbus_reset, > iic_dp_aux_reset), ^ > /usr/src/sys/sys/bus.h:747:19: note: expanded from macro 'DEVMETHOD' > #define DEVMETHOD KOBJMETHOD > ^ > /usr/src/sys/sys/kobj.h:100:5: note: expanded from macro 'KOBJMETHOD' > { &NAME##_desc, (kobjop_t) (1 ? FUNC : (NAME##_t *)NULL) } > ^ > <scratch space>:150:1: note: expanded from here > iicbus_reset_desc > ^ > /usr/src/sys/dev/drm2/drm_dp_iic_helper.c:268:2: error: expected > expression /usr/src/sys/sys/bus.h:747:19: note: expanded from macro > 'DEVMETHOD' #define DEVMETHOD KOBJMETHOD > ^ > /usr/src/sys/sys/kobj.h:100:52: note: expanded from macro 'KOBJMETHOD' > { &NAME##_desc, (kobjop_t) (1 ? FUNC : (NAME##_t *)NULL) } > ^ > /usr/src/sys/dev/drm2/drm_dp_iic_helper.c:268:2: error: use of > undeclared identifier 'iicbus_reset_t' /usr/src/sys/sys/bus.h:747:19: > note: expanded from macro 'DEVMETHOD' #define DEVMETHOD > KOBJMETHOD ^ > /usr/src/sys/sys/kobj.h:100:42: note: expanded from macro 'KOBJMETHOD' > { &NAME##_desc, (kobjop_t) (1 ? FUNC : (NAME##_t *)NULL) } > ^ > <scratch space>:151:1: note: expanded from here > iicbus_reset_t > ^ > /usr/src/sys/dev/drm2/drm_dp_iic_helper.c:269:2: error: use of > undeclared identifier 'iicbus_transfer_desc' > DEVMETHOD(iicbus_transfer, iic_dp_aux_xfer), ^ > /usr/src/sys/sys/bus.h:747:19: note: expanded from macro 'DEVMETHOD' > #define DEVMETHOD KOBJMETHOD > ^ > /usr/src/sys/sys/kobj.h:100:5: note: expanded from macro 'KOBJMETHOD' > { &NAME##_desc, (kobjop_t) (1 ? FUNC : (NAME##_t *)NULL) } > ^ > <scratch space>:152:1: note: expanded from here > iicbus_transfer_desc > ^ > /usr/src/sys/dev/drm2/drm_dp_iic_helper.c:269:2: error: expected > expression /usr/src/sys/sys/bus.h:747:19: note: expanded from macro > 'DEVMETHOD' #define DEVMETHOD KOBJMETHOD > ^ > /usr/src/sys/sys/kobj.h:100:52: note: expanded from macro 'KOBJMETHOD' > { &NAME##_desc, (kobjop_t) (1 ? FUNC : (NAME##_t *)NULL) } > ^ > /usr/src/sys/dev/drm2/drm_dp_iic_helper.c:269:2: error: use of > undeclared identifier 'iicbus_transfer_t'; did you mean > 'iicbus_transfer'? /usr/src/sys/sys/bus.h:747:19: note: expanded from > macro 'DEVMETHOD' #define DEVMETHOD KOBJMETHOD > ^ > /usr/src/sys/sys/kobj.h:100:42: note: expanded from macro 'KOBJMETHOD' > { &NAME##_desc, (kobjop_t) (1 ? FUNC : (NAME##_t *)NULL) } > ^ > <scratch space>:153:1: note: expanded from here > iicbus_transfer_t > ^ > /usr/src/sys/dev/iicbus/iiconf.h:155:5: note: 'iicbus_transfer' > declared here int iicbus_transfer(device_t bus, struct iic_msg *msgs, > uint32_t nmsgs); ^ > 14 errors generated. > [%=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D%] >=20 > <[-------------]> > # pciconf -lvc > hostb0@pci0:0:0:0: class=3D0x060000 card=3D0x024d1028 > chip=3D0x2a408086 rev=3D0x07 hdr=3D0x00 vendor =3D 'Intel Corporation' > device =3D 'Mobile 4 Series Chipset Memory Controller Hub' > class =3D bridge > subclass =3D HOST-PCI > cap 09[e0] =3D vendor (length 10) Intel cap 1 version 1 > vgapci0@pci0:0:2:0: class=3D0x030000 card=3D0x024d1028 > chip=3D0x2a428086 rev=3D0x07 hdr=3D0x00 vendor =3D 'Intel Corporation' > device =3D 'Mobile 4 Series Chipset Integrated Graphics > Controller' class =3D display > subclass =3D VGA > cap 05[90] =3D MSI supports 1 message enabled with 1 message > cap 01[d0] =3D powerspec 3 supports D0 D3 current D0 > vgapci1@pci0:0:2:1: class=3D0x038000 card=3D0x024d1028 > chip=3D0x2a438086 rev=3D0x07 hdr=3D0x00 vendor =3D 'Intel Corporation' > device =3D 'Mobile 4 Series Chipset Integrated Graphics > Controller' class =3D display > cap 01[d0] =3D powerspec 3 supports D0 D3 current D0 > none0@pci0:0:3:0: class=3D0x078000 card=3D0x024d1028 > chip=3D0x2a448086 rev=3D0x07 hdr=3D0x00 vendor =3D 'Intel Corporation' > device =3D 'Mobile 4 Series Chipset MEI Controller' > class =3D simple comms > cap 01[50] =3D powerspec 3 supports D0 D3 current D0 > cap 05[8c] =3D MSI supports 1 message, 64 bit=20 > atapci0@pci0:0:3:2: class=3D0x010185 card=3D0x024d1028 > chip=3D0x2a468086 rev=3D0x07 hdr=3D0x00 vendor =3D 'Intel Corporation' > device =3D 'Mobile 4 Series Chipset PT IDER Controller' > class =3D mass storage > subclass =3D ATA > cap 01[c8] =3D powerspec 3 supports D0 D3 current D0 > cap 05[d0] =3D MSI supports 1 message, 64 bit=20 > uart2@pci0:0:3:3: class=3D0x070002 card=3D0x024d1028 > chip=3D0x2a478086 rev=3D0x07 hdr=3D0x00 vendor =3D 'Intel Corporation' > device =3D 'Mobile 4 Series Chipset AMT SOL Redirection' > class =3D simple comms > subclass =3D UART > cap 01[c8] =3D powerspec 3 supports D0 D3 current D0 > cap 05[d0] =3D MSI supports 1 message, 64 bit enabled with 1 message > em0@pci0:0:25:0: class=3D0x020000 card=3D0x024d1028 chip=3D0x10f58086 > rev=3D0x03 hdr=3D0x00 vendor =3D 'Intel Corporation' > device =3D '82567LM Gigabit Network Connection' > class =3D network > subclass =3D ethernet > cap 01[c8] =3D powerspec 2 supports D0 D3 current D0 > cap 05[d0] =3D MSI supports 1 message, 64 bit enabled with 1 message > cap 13[e0] =3D PCI Advanced Features: FLR TP > uhci0@pci0:0:26:0: class=3D0x0c0300 card=3D0x024d1028 > chip=3D0x29378086 rev=3D0x03 hdr=3D0x00 vendor =3D 'Intel Corporation' > device =3D '82801I (ICH9 Family) USB UHCI Controller' > class =3D serial bus > subclass =3D USB > cap 13[50] =3D PCI Advanced Features: FLR TP > uhci1@pci0:0:26:1: class=3D0x0c0300 card=3D0x024d1028 > chip=3D0x29388086 rev=3D0x03 hdr=3D0x00 vendor =3D 'Intel Corporation' > device =3D '82801I (ICH9 Family) USB UHCI Controller' > class =3D serial bus > subclass =3D USB > cap 13[50] =3D PCI Advanced Features: FLR TP > uhci2@pci0:0:26:2: class=3D0x0c0300 card=3D0x024d1028 > chip=3D0x29398086 rev=3D0x03 hdr=3D0x00 vendor =3D 'Intel Corporation' > device =3D '82801I (ICH9 Family) USB UHCI Controller' > class =3D serial bus > subclass =3D USB > cap 13[50] =3D PCI Advanced Features: FLR TP > ehci0@pci0:0:26:7: class=3D0x0c0320 card=3D0x024d1028 > chip=3D0x293c8086 rev=3D0x03 hdr=3D0x00 vendor =3D 'Intel Corporation' > device =3D '82801I (ICH9 Family) USB2 EHCI Controller' > class =3D serial bus > subclass =3D USB > cap 01[50] =3D powerspec 2 supports D0 D3 current D0 > cap 0a[58] =3D EHCI Debug Port at offset 0xa0 in map 0x14 > cap 13[98] =3D PCI Advanced Features: FLR TP > hdac0@pci0:0:27:0: class=3D0x040300 card=3D0x024d1028 > chip=3D0x293e8086 rev=3D0x03 hdr=3D0x00 vendor =3D 'Intel Corporation' > device =3D '82801I (ICH9 Family) HD Audio Controller' > class =3D multimedia > subclass =3D HDA > cap 01[50] =3D powerspec 2 supports D0 D3 current D0 > cap 05[60] =3D MSI supports 1 message, 64 bit enabled with 1 message > cap 10[70] =3D PCI-Express 1 root endpoint max data 128(128) FLR NS > ecap 0002[100] =3D VC 1 max VC1 > ecap 0005[130] =3D Root Complex Link Declaration 1 > pcib1@pci0:0:28:0: class=3D0x060400 card=3D0x024d1028 > chip=3D0x29408086 rev=3D0x03 hdr=3D0x01 vendor =3D 'Intel Corporation' > device =3D '82801I (ICH9 Family) PCI Express Port 1' > class =3D bridge > subclass =3D PCI-PCI > cap 10[40] =3D PCI-Express 1 root port max data 128(128) > link x0(x1) speed 0.0(2.5) ASPM disabled(L0s/L1) > slot 0 power limit 65 mW HotPlug(empty) surprise > cap 05[80] =3D MSI supports 1 message enabled with 1 message > cap 0d[90] =3D PCI Bridge card=3D0x024d1028 > cap 01[a0] =3D powerspec 2 supports D0 D3 current D0 > ecap 0002[100] =3D VC 1 max VC0 > ecap 0005[180] =3D Root Complex Link Declaration 1 > pcib2@pci0:0:28:3: class=3D0x060400 card=3D0x024d1028 > chip=3D0x29468086 rev=3D0x03 hdr=3D0x01 vendor =3D 'Intel Corporation' > device =3D '82801I (ICH9 Family) PCI Express Port 4' > class =3D bridge > subclass =3D PCI-PCI > cap 10[40] =3D PCI-Express 1 root port max data 128(128) > link x0(x1) speed 0.0(2.5) ASPM disabled(L0s/L1) > slot 3 power limit 65 mW HotPlug(empty) surprise > cap 05[80] =3D MSI supports 1 message enabled with 1 message > cap 0d[90] =3D PCI Bridge card=3D0x024d1028 > cap 01[a0] =3D powerspec 2 supports D0 D3 current D0 > ecap 0002[100] =3D VC 1 max VC0 > ecap 0005[180] =3D Root Complex Link Declaration 1 > uhci3@pci0:0:29:0: class=3D0x0c0300 card=3D0x024d1028 > chip=3D0x29348086 rev=3D0x03 hdr=3D0x00 vendor =3D 'Intel Corporation' > device =3D '82801I (ICH9 Family) USB UHCI Controller' > class =3D serial bus > subclass =3D USB > cap 13[50] =3D PCI Advanced Features: FLR TP > uhci4@pci0:0:29:1: class=3D0x0c0300 card=3D0x024d1028 > chip=3D0x29358086 rev=3D0x03 hdr=3D0x00 vendor =3D 'Intel Corporation' > device =3D '82801I (ICH9 Family) USB UHCI Controller' > class =3D serial bus > subclass =3D USB > cap 13[50] =3D PCI Advanced Features: FLR TP > uhci5@pci0:0:29:2: class=3D0x0c0300 card=3D0x024d1028 > chip=3D0x29368086 rev=3D0x03 hdr=3D0x00 vendor =3D 'Intel Corporation' > device =3D '82801I (ICH9 Family) USB UHCI Controller' > class =3D serial bus > subclass =3D USB > cap 13[50] =3D PCI Advanced Features: FLR TP > ehci1@pci0:0:29:7: class=3D0x0c0320 card=3D0x024d1028 > chip=3D0x293a8086 rev=3D0x03 hdr=3D0x00 vendor =3D 'Intel Corporation' > device =3D '82801I (ICH9 Family) USB2 EHCI Controller' > class =3D serial bus > subclass =3D USB > cap 01[50] =3D powerspec 2 supports D0 D3 current D0 > cap 0a[58] =3D EHCI Debug Port at offset 0xa0 in map 0x14 > cap 13[98] =3D PCI Advanced Features: FLR TP > pcib3@pci0:0:30:0: class=3D0x060401 card=3D0x024d1028 > chip=3D0x24488086 rev=3D0x93 hdr=3D0x01 vendor =3D 'Intel Corporation' > device =3D '82801 Mobile PCI Bridge' > class =3D bridge > subclass =3D PCI-PCI > cap 0d[50] =3D PCI Bridge card=3D0x024d1028 > isab0@pci0:0:31:0: class=3D0x060100 card=3D0x024d1028 > chip=3D0x29178086 rev=3D0x03 hdr=3D0x00 vendor =3D 'Intel Corporation' > device =3D 'ICH9M-E LPC Interface Controller' > class =3D bridge > subclass =3D PCI-ISA > cap 09[e0] =3D vendor (length 12) Intel cap 1 version 0 > features: SATA RAID-5, Mobile, 4 PCI-e x1 slots > ahci0@pci0:0:31:2: class=3D0x010601 card=3D0x024d1028 > chip=3D0x29298086 rev=3D0x03 hdr=3D0x00 vendor =3D 'Intel Corporation' > device =3D '82801IBM/IEM (ICH9M/ICH9M-E) 4 port SATA Controller > [AHCI mode]' class =3D mass storage > subclass =3D SATA > cap 05[80] =3D MSI supports 16 messages enabled with 16 messages > cap 01[70] =3D powerspec 3 supports D0 D3 current D0 > cap 12[a8] =3D SATA Index-Data Pair > cap 13[b0] =3D PCI Advanced Features: FLR TP > none1@pci0:0:31:3: class=3D0x0c0500 card=3D0x024d1028 > chip=3D0x29308086 rev=3D0x03 hdr=3D0x00 vendor =3D 'Intel Corporation' > device =3D '82801I (ICH9 Family) SMBus Controller' > class =3D serial bus > subclass =3D SMBus > <[-------------]> >=20 > [=3D> END <=3D] =20
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