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Date: Thu, 19 Dec 2013 14:14:26 +0100
From: Olivier Houchard <mlfbsd@ci0.org>
To: Wojciech Macek <wma@semihalf.com>
Subject: Re: arm SMP on Cortex-A15
Message-ID: <20131219131426.GA17686@ci0.org>
References: <CANsEV8euHTsfviiCMP_aet3qYiK2T-oK+-37eay7zAPH2S2vaA@mail.gmail.com>
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Hi Wojciech,

On Thu, Dec 19, 2013 at 12:41:59PM +0100, Wojciech Macek wrote:
> Hi,
> 
> Finally, I'm able to run FreeBSD stable on Cortex-A15. The TLB issue which
> was observed, was caused by an aggressive A15 feature called "L2 TLB
> prefetch".
> 

Wow that's great news !

> There are 4 fixes that helped:
> 0. Prerequisite, Olivier's patch for PCPU atomicity.

Cool, I'll commit it, then.

> 1. TEX remap - to be compliant with spec, TEX remap is used to configure
> memory as Inner Shareable
> 2. TLB flush SE - after each PTE modification and PTE_SYNC, there is no
> guarantee that newly created entry is not overlapped by old value in TLB
> cache. Do flush_SE to ensure proper mapping.

Wow, I failed to realized we were missing so many flush. And I've read the
pmap code to find any of those many many times. Great work !


> 3. During context switch, ensure that tlb flush is executed after ttb is
> changed. Clean BTB to be compliant with specs.
> 
> Above patches can be found here
> https://drive.google.com/folderview?id=0B-7yTLrPxaWteWFtWUQxVVNHVFk&usp=sharing
> 
> 
> None of them is 100%-ready, but should work. Any comments and/or testing
> are really appreciated.
> 

Regards,

Olivier