Date: Thu, 10 Sep 2015 05:40:01 +0000 From: Alexey Dokuchaev <danfe@FreeBSD.org> To: Jan Beich <jbeich@FreeBSD.org> Cc: ports-committers@freebsd.org, svn-ports-all@freebsd.org, svn-ports-head@freebsd.org Subject: Re: svn commit: r396521 - in head/lang/mosh: . files Message-ID: <20150910054001.GA22038@FreeBSD.org> In-Reply-To: <1te7-bczr-wny@FreeBSD.org> References: <201509091726.t89HQETZ003966@repo.freebsd.org> <1te7-bczr-wny@FreeBSD.org>
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On Wed, Sep 09, 2015 at 09:37:28PM +0200, Jan Beich wrote:
> Alexey Dokuchaev <danfe@FreeBSD.org> writes:
>
> > - Propagate available SIMD support down to the compiler (x86 only)
> [...]
> > +.if ${MACHINE_CPU:Msse3}
> > +CONFIGURE_ENV+= MOSH_OPTS="-msse3 -mfpmath=sse"
> > +.elif ${MACHINE_CPU:Msse2}
> > +CONFIGURE_ENV+= MOSH_OPTS="-msse2 -mfpmath=sse"
> > +.elif ${MACHINE_CPU:Msse}
> > +CONFIGURE_ENV+= MOSH_OPTS="-msse -mfpmath=sse"
> > +.elif ${MACHINE_CPU:Mmmx}
> > +CONFIGURE_ENV+= MOSH_OPTS="-mmmx"
> > .endif
>
> Why add cargo cult optimization? Nothing in i?86 code seems to rely on
> __SSE* defines or *intrin.h.
This part pretty closely matches similar code in configure script (linux
case branch) which detects SIMD features via /proc/cpuinfo, so I simply
ported it assuming that authors knew what they were doing.
Now that I think more about it, vectorization in GCC is enabled at -O3
which explains why it was there by default, but as I'd removed I'd also
inadvertently cancelled the effect of -mfoo options. O_o
On the other hand, setting CPUTYPE in /etc/make.conf will be propagated
as an -march which should be enough (e.g. -march=nocona implies -msse3).
I'll think/play with the code a bit more and likely remove it; thanks for
bring it to attention.
> Besides, -mfpmath=sse, -msse2 and -msse are default on amd64 which means
> the following chunk is always enabled:
>
> // [...]/libatomic_ops/src/atomic_ops/sysdeps/standard_ao_double_t.h
> #if (defined(__x86_64__) && defined(__GNUC__)) || defined(_WIN64)
> # include <xmmintrin.h>
> typedef __m128 double_ptr_storage;
True, at least I've should've made that block conditional on i386 (keep
forgetting that we also have amd64 now). It is largely non-standard
architecture for me (despite being Tier-1); all my local gear is 32-bit.
I think it can be useful to some people because of >4G memory support
and much less register pressure to get clener and faster code though.
./danfe
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