Date: Fri, 12 May 2023 14:51:00 +0000 From: Souradeep Chakrabarti <schakrabarti@microsoft.com> To: Kyle Evans <kevans@freebsd.org> Cc: Wei Hu <weh@microsoft.com>, "freebsd-hackers@FreeBSD.org" <freebsd-hackers@freebsd.org> Subject: RE: enabling same PPI interrupt to all CPU in ARM64 SMP Message-ID: <PSAP153MB0536DF73D2FE339840F4D8DACC759@PSAP153MB0536.APCP153.PROD.OUTLOOK.COM> In-Reply-To: <KL1P15301MB053251337F40AE212142E1E1CC719@KL1P15301MB0532.APCP153.PROD.OUTLOOK.COM> References: <KL1P15301MB053251337F40AE212142E1E1CC719@KL1P15301MB0532.APCP153.PROD.OUTLOOK.COM>
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>-----Original Message----- >From: Souradeep Chakrabarti >Sent: Monday, May 8, 2023 6:39 PM >To: Kyle Evans <kevans@freebsd.org> >Cc: Wei Hu <weh@microsoft.com>; freebsd-hackers@FreeBSD.org >Subject: enabling same PPI interrupt to all CPU in ARM64 SMP > >Hi , > >While using SMP in ARM64 Hyper-V we are getting stuck in boot if there is = a >interrupt for VMBus coming to CPU1 and VMBus interrupt handler is not gett= ing >that interrupt. > >In ARM64 Hyper-V we are using IRQ18 for VMBus and it is a PPI interrupt. > >But Hypev-V host sends interrupt to this IRQ 18 for both CPU0 and CPU1 in = 2CPU >system. >This is based on the corresponding VMBus channel which assigned with the C= PU. > >Now VMBus ISR is getting the interrupt in CPU0 but not getting from CPU1. >Any idea, how we can use the same PPI 18 for all the CPU cores? > >Any help will be appreciated, as this is blocking the enablement of FreeBS= D in Azure >ARM64. [Souradeep]=20 Can someone please help me it.=20 > >Thanks, >Souradeep >
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