From owner-freebsd-hackers@FreeBSD.ORG Thu Oct 24 07:05:01 2013 Return-Path: Delivered-To: freebsd-hackers@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTP id E41C7293; Thu, 24 Oct 2013 07:05:01 +0000 (UTC) (envelope-from shrikanth07@gmail.com) Received: from mail-ve0-x22d.google.com (mail-ve0-x22d.google.com [IPv6:2607:f8b0:400c:c01::22d]) (using TLSv1 with cipher ECDHE-RSA-RC4-SHA (128/128 bits)) (No client certificate requested) by mx1.freebsd.org (Postfix) with ESMTPS id 971B82EF1; Thu, 24 Oct 2013 07:05:01 +0000 (UTC) Received: by mail-ve0-f173.google.com with SMTP id jw12so1103170veb.18 for ; Thu, 24 Oct 2013 00:05:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:date:message-id:subject:from:to:content-type; bh=bMqm/z9FR+HfH2VkKSR9IxJL7CawKYPiRbKKEbFYvTg=; b=XGg/t0zC1ZlrJKGMiNCIimJ/055rIUWa6b5wAMSTz0bWXlTCRxNLNCXzXWq8/xfUsD de09ICf9++L1zqJImA2FaR6f3f594KHL3HxR8KHazK/h80WcpU8LdjWLGsaeo1B69MFU sn8esmdLvc/NHRxC7EtI1aqRGs88mSpdTCxlWO7cKziolIiYVGv7H5iu3tMjsBILirol eQTpxYTJe/x0zVUriOaGidbHsVV4ZAz/Ud85FFjvTFsMCBUVoaG026/V0m3iu505kFly Q/oTUvluhnC2AwQ7VdRJ4RHK1jT9NmHqPXV1qJKFQ4ivkxh3LqBfNO6TA3vzxZJg6ori v6yw== MIME-Version: 1.0 X-Received: by 10.52.230.102 with SMTP id sx6mr543021vdc.15.1382598300695; Thu, 24 Oct 2013 00:05:00 -0700 (PDT) Received: by 10.58.133.131 with HTTP; Thu, 24 Oct 2013 00:05:00 -0700 (PDT) Date: Thu, 24 Oct 2013 00:05:00 -0700 Message-ID: Subject: FreeBSD Machine check architecture and memory controller hub chipset From: Shrikanth Kamath To: freebsd-hackers@freebsd.org, freebsd-i386@freebsd.org Content-Type: text/plain; charset=ISO-8859-1 X-BeenThere: freebsd-hackers@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Technical Discussions relating to FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 24 Oct 2013 07:05:02 -0000 The mca_check_status function checks the status of the Intel MCA registers to generate the mca records. When reporting compound error codes which indicate memory errors, does the memory controller hub chipset (say e.g Intel E7320 MCH is the participating memory controller) registers need to be set to assist the processor to generate the compound error codes corresponding to errors from memory controller? I want to be able to extend the mca_scan function to scan the memory controller hub chipset registers if this compound error code were to be generated. Reference, section 15.9.2 in Intel 64 and IA-32 architectures software developers manual (Vol 3). -- Shrikanth R K