From owner-freebsd-arm@FreeBSD.ORG Thu Aug 23 23:59:17 2012 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 458DC106566B; Thu, 23 Aug 2012 23:59:17 +0000 (UTC) (envelope-from adrian.chadd@gmail.com) Received: from mail-pb0-f54.google.com (mail-pb0-f54.google.com [209.85.160.54]) by mx1.freebsd.org (Postfix) with ESMTP id 0784E8FC15; Thu, 23 Aug 2012 23:59:16 +0000 (UTC) Received: by pbbrp2 with SMTP id rp2so2439273pbb.13 for ; Thu, 23 Aug 2012 16:59:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type; bh=bVpnJB73bCLefXPcIvjYhYqKlLLMR3NxqYPJzQo36bs=; b=l37Rd9vmQ/ynZvNsTSwDhK9YQVWXfbu3PrJPR6iGT/dxcAkV0v74ykjudVMxy4x9aM WQy/q8uvDFSJNXPiXtsWxCMW+oMzZoHCj+QDu153Vlr7uZs96ZrrcvurLW2Zk8jmM0Qg ynnQeJ3vNToaY8rJOte5Khe+34yMmsXk1j6N1v/1jHpK2TTD4ogFT6O81cvcKkc1J43y EFdZZjIxsDmwwXp+MgBY9UTRqFgcu16kkPXb/S01nH+a7NQqIOkS9cCsOoMTHgcyWuGe Z1ZdsSqGNOEmFWiFaxgY2u8yhwhV7czSYeJiA7uHYMWB8I0evjvDowD0FOmtmkCOrzwe oXyw== MIME-Version: 1.0 Received: by 10.68.138.169 with SMTP id qr9mr8493185pbb.27.1345766356862; Thu, 23 Aug 2012 16:59:16 -0700 (PDT) Sender: adrian.chadd@gmail.com Received: by 10.68.36.106 with HTTP; Thu, 23 Aug 2012 16:59:16 -0700 (PDT) In-Reply-To: <1345766109.27688.606.camel@revolution.hippie.lan> References: <1345757300.27688.535.camel@revolution.hippie.lan> <3A08EB08-2BBF-4B0F-97F2-A3264754C4B7@bsdimp.com> <1345763393.27688.578.camel@revolution.hippie.lan> <1345765503.27688.602.camel@revolution.hippie.lan> <1345766109.27688.606.camel@revolution.hippie.lan> Date: Thu, 23 Aug 2012 16:59:16 -0700 X-Google-Sender-Auth: lfQnLTGTsXKt1gXoEwgg8ou0Azs Message-ID: From: Adrian Chadd To: Ian Lepore Content-Type: text/plain; charset=ISO-8859-1 Cc: freebsd-arm@freebsd.org, freebsd-mips@freebsd.org, freebsd-arch@freebsd.org Subject: Re: Partial cacheline flush problems on ARM and MIPS X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 23 Aug 2012 23:59:17 -0000 On 23 August 2012 16:55, Ian Lepore wrote: >> In what case though would the hardware say it can only DMA on a 64k >> alignment BUT move one byte at a time? Then what would the starting >> address be for each DMA? >> > > Maybe the device has a reduced number of address bits in its registers > and the low-order bits always start at zero and increment internally in > a wider register so that any length dma can happen, but it has to start > on a 64k boundary. > > Maybe the address you pass it has to be a 64k boundary, but then the > bytes actually end up in one-of-N slots within that 64k region, based on > other parameters of the transfer. > > I've worked with some strange hardware over the years. Right. That's pretty odd though. But now I understand where you're coming from. I still think the short term solution should be "fix the USB stack to not do that!" The longer term problem is likely to figure out what makes sense. Eg, if you're going to allow the allocator to interleave 16 byte chunks (on a 32 byte cache line platform) with some being DMA buffers and others being non-DMA buffers; or whether you enforce that the whole chunk is a DMA buffer for your hardware and you look after it, or something else.. Adrian