From nobody Tue Mar 31 10:51:32 2026 X-Original-To: bugs@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4flQ0N4ny3z6X03Z for ; Tue, 31 Mar 2026 10:51:32 +0000 (UTC) (envelope-from bugzilla-noreply@freebsd.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R12" (not verified)) by mx1.freebsd.org (Postfix) with ESMTPS id 4flQ0N1f2Wz41wL for ; Tue, 31 Mar 2026 10:51:32 +0000 (UTC) (envelope-from bugzilla-noreply@freebsd.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1774954292; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=8p2QdI25SIupkHSulU3yOZdt09EJYqQ2aJHJvEhx3BA=; b=pIIuQGcNY4d64y9ctVacRVIuMDfGjw6ZzWFGZ61DK2Gj0cld6nrAJMsfVDFger1rMEZd3C CCSxwY1YK2bHJegQe2D93UbljyQ51N09TX5py9wdsklrm3iLnTVG5S/fZWvd3bZcZGvsCR 836Ws907Za+7cE09cNrhLI/SD0nl6YVqxqCkmJK+CNV6P2Buv7Ag6hL2x3OYCpPjKrokt6 Y+XBHTySFyKNC4swJjC024ZYT6xzQCgX1N7xCzv6HQK8iyMEWE2nBXeIuqr5sJW9L6q7xh csDF3JuaPcr6nlSay4nzXRpwRi+4ZX2DS9gJw8bZ2UnJuTxFdUXs6t/ym42AbA== ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1774954292; a=rsa-sha256; cv=none; b=G9HoZ731AJzTFinExijg4FxJNEe1MJ3+cvsy2NTLOdIwJmR6/Mw/8OUGoiE7Uh+0zKRJKA ZPRc0CBQlUrrvfsoCLuLSmOCeg1F9gfrcrnTnw2Bd9KB000XH9GjfTXdRXNoJtn936O9Co kKNn3Gji/GtJD3DK+ZUekAzkgq0osowc7LqgtSEOIUFyYhi12Fv5haDeBxHsmRvxSaP1/a es1tqCCkoD4K4xmy85K7RqGkOuzbxA01ACev5GLzlCXKP56pPMLeRDmKo8QkXUT29oa+m0 dyxMYcwIlrt5iV2o47FNKujccY6RFT8kq2ZZOsd7r3f1QPwf051b879yExewTw== ARC-Authentication-Results: i=1; mx1.freebsd.org; none ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1774954292; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=8p2QdI25SIupkHSulU3yOZdt09EJYqQ2aJHJvEhx3BA=; b=hFEqR3LftvFpSDhKMENgA0WZGiJ8WitTOHv5TyMKwsWUFXPmJqSKR4NDmonC5QGR33gOuc ia48KC+2flWkOF5EB07bS0fwiD0079QfQdXjAV4Zodl5mJIuZgBq2OMO5pZQGT1ob0J+c1 zpgDrhYwNJ9FLqYhTdthOyhZYEFIOO7nfTrjJTk9yUqhoEJa14AYXQ8wgN8LVNBaQXY1Hj NEU8HxH+RcoD991cRsy5vN30L13F05n76OHn0bVIOHJ9D8p+a6vwhlc/+dtZ5d1sx2OPqI GN7VT+qtPQSCyzhaDdngCqdAxa5WIEBHlpVP5XuVgN0Uux1cuu9ueJg3wmPSig== Received: from kenobi.freebsd.org (kenobi.freebsd.org [IPv6:2610:1c1:1:606c::50:1d]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 4flQ0N15XXz99Y for ; Tue, 31 Mar 2026 10:51:32 +0000 (UTC) (envelope-from bugzilla-noreply@freebsd.org) Received: from kenobi.freebsd.org ([127.0.1.5]) by kenobi.freebsd.org (8.15.2/8.15.2) with ESMTP id 62VApWO4086124 for ; Tue, 31 Mar 2026 10:51:32 GMT (envelope-from bugzilla-noreply@freebsd.org) Received: (from www@localhost) by kenobi.freebsd.org (8.15.2/8.15.2/Submit) id 62VApWKO086123 for bugs@FreeBSD.org; Tue, 31 Mar 2026 10:51:32 GMT (envelope-from bugzilla-noreply@freebsd.org) X-Authentication-Warning: kenobi.freebsd.org: www set sender to bugzilla-noreply@freebsd.org using -f From: bugzilla-noreply@freebsd.org To: bugs@FreeBSD.org Subject: [Bug 293382] Dead lock and kernel crash around closefp_impl Date: Tue, 31 Mar 2026 10:51:32 +0000 X-Bugzilla-Reason: AssignedTo X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: Base System X-Bugzilla-Component: kern X-Bugzilla-Version: 14.3-STABLE X-Bugzilla-Keywords: crash X-Bugzilla-Severity: Affects Only Me X-Bugzilla-Who: devgs@ukr.net X-Bugzilla-Status: Open X-Bugzilla-Resolution: X-Bugzilla-Priority: --- X-Bugzilla-Assigned-To: bugs@FreeBSD.org X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="UTF-8" X-Bugzilla-URL: https://bugs.freebsd.org/bugzilla/ Auto-Submitted: auto-generated List-Id: Bug reports List-Archive: https://lists.freebsd.org/archives/freebsd-bugs List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-freebsd-bugs@FreeBSD.org MIME-Version: 1.0 https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=3D293382 --- Comment #37 from Paul --- I see, sorry for pushing my bad analysis. This is a pretty recent (and decent) CPU. We are using it on many other ser= vers with a bit different kind of load (not that many open sockets per process),= but with much more stress overall. And only in this case the issue occurs. Doub= tful that's the CPU hardware bug. We will now be applying you latest patch, than= ks for helping! # cpuid-etallen -1 CPU: vendor_id =3D "AuthenticAMD" version information (1/eax): processor type =3D primary processor (0) family =3D 0xf (15) model =3D 0x2 (2) stepping id =3D 0x1 (1) extended family =3D 0xb (11) extended model =3D 0x0 (0) (family synth) =3D 0x1a (26) (model synth) =3D 0x2 (2) miscellaneous (1/ebx): process local APIC physical ID =3D 0x33 (51) maximum IDs for CPUs in pkg =3D 0x20 (32) CLFLUSH line size =3D 0x8 (8) brand index =3D 0x0 (0) brand id =3D 0x00 (0): unknown feature information (1/edx): x87 FPU on chip =3D true VME: virtual-8086 mode enhancement =3D true DE: debugging extensions =3D true PSE: page size extensions =3D true TSC: time stamp counter =3D true RDMSR and WRMSR support =3D true PAE: physical address extensions =3D true MCE: machine check exception =3D true CMPXCHG8B inst. =3D true APIC on chip =3D true SYSENTER and SYSEXIT =3D true MTRR: memory type range registers =3D true PTE global bit =3D true MCA: machine check architecture =3D true CMOV: conditional move/compare instr =3D true PAT: page attribute table =3D true PSE-36: page size extension =3D true PSN: processor serial number =3D false CLFLUSH instruction =3D true DS: debug store =3D false ACPI: thermal monitor and clock ctrl =3D false MMX Technology =3D true FXSAVE/FXRSTOR =3D true SSE extensions =3D true SSE2 extensions =3D true SS: self snoop =3D false hyper-threading / multi-core supported =3D true TM: therm. monitor =3D false IA64 =3D false PBE: pending break event =3D false feature information (1/ecx): PNI/SSE3: Prescott New Instructions =3D true PCLMULDQ instruction =3D true DTES64: 64-bit debug store =3D false MONITOR/MWAIT =3D true CPL-qualified debug store =3D false VMX: virtual machine extensions =3D false SMX: safer mode extensions =3D false Enhanced Intel SpeedStep Technology =3D false TM2: thermal monitor 2 =3D false SSSE3 extensions =3D true context ID: adaptive or shared L1 data =3D false SDBG: IA32_DEBUG_INTERFACE =3D false FMA instruction =3D true CMPXCHG16B instruction =3D true xTPR disable =3D false PDCM: perfmon and debug =3D false PCID: process context identifiers =3D true DCA: direct cache access =3D false SSE4.1 extensions =3D true SSE4.2 extensions =3D true x2APIC: extended xAPIC support =3D true MOVBE instruction =3D true POPCNT instruction =3D true time stamp counter deadline =3D false AES instruction =3D true XSAVE/XSTOR states =3D true OS-enabled XSAVE/XSTOR =3D true AVX: advanced vector extensions =3D true F16C half-precision convert instruction =3D true RDRAND instruction =3D true hypervisor guest status =3D false cache and TLB information (2): processor serial number =3D 00B0-0F21-0000-0000-0000-0000 deterministic cache parameters (4): --- cache 0 --- cache type =3D no more caches (0) MONITOR/MWAIT (5): smallest monitor-line size (bytes) =3D 0x40 (64) largest monitor-line size (bytes) =3D 0x40 (64) enum of Monitor-MWAIT exts supported =3D true supports intrs as break-event for MWAIT =3D true monitorless MWAIT supported =3D false number of C0 sub C-states using MWAIT =3D 0x1 (1) number of C1 sub C-states using MWAIT =3D 0x2 (2) number of C2 sub C-states using MWAIT =3D 0x0 (0) number of C3 sub C-states using MWAIT =3D 0x0 (0) number of C4 sub C-states using MWAIT =3D 0x0 (0) number of C5 sub C-states using MWAIT =3D 0x0 (0) number of C6 sub C-states using MWAIT =3D 0x0 (0) number of C7 sub C-states using MWAIT =3D 0x0 (0) Thermal and Power Management Features (6): digital thermometer =3D false Intel Turbo Boost Technology =3D false ARAT always running APIC timer =3D true PLN power limit notification =3D false ECMD extended clock modulation duty =3D false PTM package thermal management =3D false HWP base registers =3D false HWP notification =3D false HWP activity window =3D false HWP energy performance preference =3D false HWP package level request =3D false HDC base registers =3D false Intel Turbo Boost Max Technology 3.0 =3D false HWP capabilities =3D false HWP PECI override =3D false flexible HWP =3D false IA32_HWP_REQUEST MSR fast access mode =3D false HW_FEEDBACK MSRs supported =3D false ignoring idle logical processor HWP req =3D false IA32_HWP_CTL MSR supported =3D false Thread Director =3D false IA32_HW_FEEDBACK_THREAD_CONFIG bit 25 =3D false digital thermometer thresholds =3D 0x0 (0) hardware coordination feedback =3D true ACNT2 available =3D false performance-energy bias capability =3D false number of enh hardware feedback classes =3D 0x0 (0) performance capability reporting =3D false energy efficiency capability reporting =3D false size of feedback struct (4KB pages) =3D 0x1 (1) index of CPU's row in feedback struct =3D 0x0 (0) extended feature flags (7): FSGSBASE instructions =3D true IA32_TSC_ADJUST MSR supported =3D true SGX: Software Guard Extensions supported =3D false BMI1 instructions =3D true HLE hardware lock elision =3D false AVX2: advanced vector extensions 2 =3D true FDP_EXCPTN_ONLY =3D false SMEP supervisor mode exec protection =3D true BMI2 instructions =3D true enhanced REP MOVSB/STOSB =3D true INVPCID instruction =3D true RTM: restricted transactional memory =3D false RDT-CMT/PQoS cache monitoring =3D true deprecated FPU CS/DS =3D false MPX: intel memory protection extensions =3D false RDT-CAT/PQE cache allocation =3D true AVX512F: AVX-512 foundation instructions =3D true AVX512DQ: double & quadword instructions =3D true RDSEED instruction =3D true ADX instructions =3D true SMAP: supervisor mode access prevention =3D true AVX512IFMA: integer fused multiply add =3D true PCOMMIT instruction =3D false CLFLUSHOPT instruction =3D true CLWB instruction =3D true Intel processor trace =3D false AVX512PF: prefetch instructions =3D false AVX512ER: exponent & reciprocal instrs =3D false AVX512CD: conflict detection instrs =3D true SHA instructions =3D true AVX512BW: byte & word instructions =3D true AVX512VL: vector length =3D true PREFETCHWT1 =3D false AVX512VBMI: vector byte manipulation =3D true UMIP: user-mode instruction prevention =3D true PKU protection keys for user-mode =3D true OSPKE CR4.PKE and RDPKRU/WRPKRU =3D true WAITPKG instructions =3D false AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND =3D true CET_SS: CET shadow stack =3D true GFNI: Galois Field New Instructions =3D true VAES instructions =3D true VPCLMULQDQ instruction =3D true AVX512_VNNI: neural network instructions =3D true AVX512_BITALG: bit count/shiffle =3D true TME: Total Memory Encryption =3D false AVX512: VPOPCNTDQ instruction =3D true LA57: 57-bit addrs & 5-level paging =3D true BNDLDX/BNDSTX MAWAU value in 64-bit mode =3D 0x0 (0) RDPID: read processor ID supported =3D true KL: key locker =3D false bus lock detection =3D true CLDEMOTE supports cache line demote =3D false MOVDIRI instruction =3D true MOVDIR64B instruction =3D true ENQCMD instruction =3D false SGX_LC: SGX launch config supported =3D false PKS: supervisor protection keys =3D false SGX-KEYS: SGX attestation services =3D false AVX512_4VNNIW: neural network instrs =3D false AVX512_4FMAPS: multiply acc single prec =3D false fast short REP MOV =3D true UINTR: user interrupts =3D false AVX512_VP2INTERSECT: intersect mask regs =3D true IA32_MCU_OPT_CTRL SRBDS mitigation MSR =3D false VERW MD_CLEAR microcode support =3D false RTM transaction always aborts =3D false IA32_TSX_FORCE_ABORT MSR =3D false SERIALIZE instruction =3D false hybrid part =3D false TSXLDTRK: TSX suspend load addr tracking =3D false PCONFIG instruction =3D false LBR: architectural last branch records =3D false CET_IBT: CET indirect branch tracking =3D false AMX-BF16: tile bfloat16 support =3D false AVX512_FP16: fp16 support =3D false AMX-TILE: tile architecture support =3D false AMX-INT8: tile 8-bit integer support =3D false IBRS/IBPB: indirect branch restrictions =3D false STIBP: 1 thr indirect branch predictor =3D false L1D_FLUSH: IA32_FLUSH_CMD MSR =3D true IA32_ARCH_CAPABILITIES MSR =3D false IA32_CORE_CAPABILITIES MSR =3D false SSBD: speculative store bypass disable =3D false SHA512 instructions =3D false SM3 instructions =3D false SM4 instructions =3D false RAO-INT atomic instructions =3D false AVX-VNNI: AVX VNNI neural network instrs =3D true AVX512_BF16: bfloat16 instructions =3D true LASS: linear address space separation =3D false CMPccXADD instructions =3D false ArchPerfmonExt leaf 0x23 is valid =3D false fast zero-length REP MOVSB =3D false fast short REP STOSB =3D false fast short REP CMPSB, REP SCASB =3D false FRED transitions & MSRs =3D false LKGS instruction =3D false WRMSRNS instruction =3D false NMI-source reporting =3D false AMX-FP16: FP16 tile operations =3D false HRESET: history reset support =3D false AVX-IFMA: integer fused multiply add =3D false LAM: linear address masking =3D false RDMSRLIST, WRMSRLIST instructions =3D false INVD prevention after BIOS done =3D false MOVRS instructions =3D false IA32_PPIN & IA32_PPIN_CTL MSRs supported =3D false PBNDKB instruction =3D false IA32_MISC_ENABLE cannot limit CPUID max =3D false asymmetric RDT-M monitoring =3D false asymmetric RDT-A allocation =3D false RDMSR/WRMSRNS immediates supported =3D false AVX-VNNI-INT8 instructions =3D false AVX-NE-CONVERT instructions =3D false AMX-COMPLEX instructions =3D false AVX-VNNI-INT16 instructions =3D false user-timer events =3D false PREFETCHIT0, PREFETCHIT1 instructions =3D false URDMSR, UWRMSR instructions =3D false UIRET flexibly updates UIF =3D false CET_SSS: shadow stacks w/o page faults =3D false AVX10 instructions =3D false APX advanced performance extensions =3D false MWAIT instruction =3D false Direct Cache Access Parameters (9): PLATFORM_DCA_CAP MSR bits =3D 0 Architecture Performance Monitoring Features (0xa): version ID =3D 0x0 (0) number of counters per logical processor =3D 0x0 (0) bit width of counter =3D 0x0 (0) length of EBX bit vector =3D 0x0 (0) core cycle event =3D not available instruction retired event =3D not available reference cycles event =3D not available last-level cache ref event =3D not available last-level cache miss event =3D not available branch inst retired event =3D not available branch mispred retired event =3D not available topdown slots event =3D not available topdown backend bound =3D not available topdown bad speculation =3D not available topdown frontend bound =3D not available topdown retiring =3D not available LBR inserts =3D not available fixed counter 0 supported =3D false fixed counter 1 supported =3D false fixed counter 2 supported =3D false fixed counter 3 supported =3D false fixed counter 4 supported =3D false fixed counter 5 supported =3D false fixed counter 6 supported =3D false fixed counter 7 supported =3D false fixed counter 8 supported =3D false fixed counter 9 supported =3D false fixed counter 10 supported =3D false fixed counter 11 supported =3D false fixed counter 12 supported =3D false fixed counter 13 supported =3D false fixed counter 14 supported =3D false fixed counter 15 supported =3D false fixed counter 16 supported =3D false fixed counter 17 supported =3D false fixed counter 18 supported =3D false fixed counter 19 supported =3D false fixed counter 20 supported =3D false fixed counter 21 supported =3D false fixed counter 22 supported =3D false fixed counter 23 supported =3D false fixed counter 24 supported =3D false fixed counter 25 supported =3D false fixed counter 26 supported =3D false fixed counter 27 supported =3D false fixed counter 28 supported =3D false fixed counter 29 supported =3D false fixed counter 30 supported =3D false fixed counter 31 supported =3D false number of contiguous fixed counters =3D 0x0 (0) bit width of fixed counters =3D 0x0 (0) anythread deprecation =3D false x2APIC features / processor topology (0xb): extended APIC ID =3D 51 --- level 0 --- level number =3D 0x0 (0) level type =3D thread (1) bit width of level & previous levels =3D 0x0 (0) number of logical processors at level =3D 0x1 (1) --- level 1 --- level number =3D 0x1 (1) level type =3D core (2) bit width of level & previous levels =3D 0x7 (7) number of logical processors at level =3D 0x20 (32) --- level 2 --- level number =3D 0x2 (2) level type =3D invalid (0) bit width of level & previous levels =3D 0x0 (0) number of logical processors at level =3D 0x0 (0) XSAVE features (0xd/0): XCR0 valid bit field mask =3D 0x00000000000002e7 x87 state =3D true SSE state =3D true AVX state =3D true MPX BNDREGS =3D false MPX BNDCSR =3D false AVX-512 opmask =3D true AVX-512 ZMM_Hi256 =3D true AVX-512 Hi16_ZMM =3D true PKRU state =3D true XTILECFG state =3D false XTILEDATA state =3D false bytes required by fields in XCR0 =3D 0x00000988 (2440) bytes required by XSAVE/XRSTOR area =3D 0x00000988 (2440) XSAVEOPT instruction =3D true XSAVEC instruction =3D true XGETBV instruction =3D true XSAVES/XRSTORS instructions =3D true XFD: extended feature disable supported =3D false SAVE area size in bytes =3D 0x00000988 (2440) IA32_XSS valid bit field mask =3D 0x0000000000001800 PT state =3D false PASID state =3D false CET_U user state =3D true CET_S supervisor state =3D true HDC state =3D false UINTR state =3D false LBR state =3D false HWP state =3D false AVX/YMM features (0xd/2): AVX/YMM save state byte size =3D 0x00000100 (256) AVX/YMM save state byte offset =3D 0x00000240 (576) supported in IA32_XSS or XCR0 =3D XCR0 (user state) 64-byte alignment in compacted XSAVE =3D false XFD faulting supported =3D false AVX-512 opmask features (0xd/5): AVX-512 opmask save state byte size =3D 0x00000040 (64) AVX-512 opmask save state byte offset =3D 0x00000340 (832) supported in IA32_XSS or XCR0 =3D XCR0 (user state) 64-byte alignment in compacted XSAVE =3D false XFD faulting supported =3D false AVX-512 ZMM_Hi256 features (0xd/6): AVX-512 ZMM_Hi256 save state byte size =3D 0x00000200 (512) AVX-512 ZMM_Hi256 save state byte offset =3D 0x00000380 (896) supported in IA32_XSS or XCR0 =3D XCR0 (user state) 64-byte alignment in compacted XSAVE =3D false XFD faulting supported =3D false AVX-512 Hi16_ZMM features (0xd/7): AVX-512 Hi16_ZMM save state byte size =3D 0x00000400 (1024) AVX-512 Hi16_ZMM save state byte offset =3D 0x00000580 (1408) supported in IA32_XSS or XCR0 =3D XCR0 (user state) 64-byte alignment in compacted XSAVE =3D false XFD faulting supported =3D false PKRU features (0xd/9): PKRU save state byte size =3D 0x00000008 (8) PKRU save state byte offset =3D 0x00000980 (2432) supported in IA32_XSS or XCR0 =3D XCR0 (user state) 64-byte alignment in compacted XSAVE =3D false XFD faulting supported =3D false CET_U user features (0xd/0xb): CET_U user save state byte size =3D 0x00000010 (16) CET_U user save state byte offset =3D 0x00000000 (0) supported in IA32_XSS or XCR0 =3D IA32_XSS (supervisor sta= te) 64-byte alignment in compacted XSAVE =3D false XFD faulting supported =3D false CET_S supervisor features (0xd/0xc): CET_S supervisor save state byte size =3D 0x00000018 (24) CET_S supervisor save state byte offset =3D 0x00000000 (0) supported in IA32_XSS or XCR0 =3D IA32_XSS (supervisor sta= te) 64-byte alignment in compacted XSAVE =3D false XFD faulting supported =3D false Quality of Service Monitoring Resource Type (0xf/0): Maximum range of RMID =3D 4095 supports L3 cache monitoring =3D true L3 Cache Quality of Service Monitoring (0xf/1): Conversion factor from IA32_QM_CTR to bytes =3D 64 Maximum range of RMID =3D 4095 Counter width =3D 44 QoS monitoring counter size =3D 0x2c (44) IA32_QM_CTR bit 61 is overflow =3D false non-CPU agent cache monitoring (CMT) =3D false non-CPU agent mem bandwidth mon (MBM) =3D false (QoS monitoring counter size synth) =3D 44 supports L3 occupancy monitoring =3D true supports L3 total bandwidth monitoring =3D true supports L3 local bandwidth monitoring =3D true Resource Director Technology Allocation (0x10/0): L3 cache allocation technology supported =3D true L2 cache allocation technology supported =3D false memory bandwidth allocation supported =3D false cache bandwidth allocation supported =3D false L3 Cache Allocation Technology (0x10/1): length of capacity bit mask =3D 0x10 (16) Bit-granular map of isolation/contention =3D 0x00000000 non-CPU agent support =3D false code and data prioritization supported =3D true non-contiguous bitmask supported =3D false highest COS number supported =3D 0xf (15) extended processor signature (0x80000001/eax): family/generation =3D 0xf (15) model =3D 0x2 (2) stepping id =3D 0x1 (1) extended family =3D 0xb (11) extended model =3D 0x0 (0) (family synth) =3D 0x1a (26) (model synth) =3D 0x2 (2) extended feature flags (0x80000001/edx): x87 FPU on chip =3D true virtual-8086 mode enhancement =3D true debugging extensions =3D true page size extensions =3D true time stamp counter =3D true RDMSR and WRMSR support =3D true physical address extensions =3D true machine check exception =3D true CMPXCHG8B inst. =3D true APIC on chip =3D true SYSCALL and SYSRET instructions =3D true memory type range registers =3D true global paging extension =3D true machine check architecture =3D true conditional move/compare instruction =3D true page attribute table =3D true page size extension =3D true multiprocessing capable =3D false no-execute page protection =3D true AMD multimedia instruction extensions =3D true MMX Technology =3D true FXSAVE/FXRSTOR =3D true SSE extensions =3D true 1-GB large page support =3D true RDTSCP =3D true long mode (AA-64) =3D true 3DNow! instruction extensions =3D false 3DNow! instructions =3D false extended brand id (0x80000001/ebx): raw =3D 0x40000000 (1073741824) BrandId =3D 0x0 (0) PkgType =3D 0x4 (4) AMD feature flags (0x80000001/ecx): LAHF/SAHF supported in 64-bit mode =3D true CMP Legacy =3D true SVM: secure virtual machine =3D true extended APIC space =3D true AltMovCr8 =3D true LZCNT advanced bit manipulation =3D true SSE4A support =3D true misaligned SSE mode =3D true 3DNow! PREFETCH/PREFETCHW instructions =3D true OS visible workaround =3D true instruction based sampling =3D true XOP support =3D false SKINIT/STGI support =3D true watchdog timer support =3D true lightweight profiling support =3D false 4-operand FMA instruction =3D false TCE: translation cache extension =3D true NodeId MSR C001100C =3D false TBM support =3D false topology extensions =3D true core performance counter extensions =3D true NB/DF performance counter extensions =3D true data breakpoint extension =3D true performance time-stamp counter support =3D false LLC performance counter extensions =3D true MWAITX/MONITORX supported =3D true Address mask extension support =3D true brand =3D "AMD EPYC 9355 32-Core Processor " L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax): instruction # entries =3D 0x40 (64) instruction associativity =3D 0xff (255) data # entries =3D 0x60 (96) data associativity =3D 0xff (255) L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx): instruction # entries =3D 0x40 (64) instruction associativity =3D 0xff (255) data # entries =3D 0x60 (96) data associativity =3D 0xff (255) L1 data cache information (0x80000005/ecx): line size (bytes) =3D 0x40 (64) lines per tag =3D 0x1 (1) associativity =3D 0xc (12) size (KB) =3D 0x30 (48) L1 instruction cache information (0x80000005/edx): line size (bytes) =3D 0x40 (64) lines per tag =3D 0x1 (1) associativity =3D 0x8 (8) size (KB) =3D 0x20 (32) L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax): instruction # entries =3D 0x40 (64) instruction associativity =3D 2-way (2) data # entries =3D 0x80 (128) data associativity =3D 4 to 5-way (4) L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx): instruction # entries =3D 0x40 (64) instruction associativity =3D 4 to 5-way (4) data # entries =3D 0x80 (128) data associativity =3D 8 to 15-way (6) L2 unified cache information (0x80000006/ecx): line size (bytes) =3D 0x40 (64) lines per tag =3D 0x1 (1) associativity =3D 16 to 31-way (8) size (KB) =3D 0x400 (1024) L3 cache information (0x80000006/edx): line size (bytes) =3D 0x40 (64) lines per tag =3D 0x1 (1) associativity =3D 0x9 (9) size (in 512KB units) =3D 0x200 (512) RAS Capability (0x80000007/ebx): MCA overflow recovery support =3D true SUCCOR support =3D true HWA: hardware assert support =3D false scalable MCA support =3D true Advanced Power Management Features (0x80000007/ecx): CmpUnitPwrSampleTimeRatio =3D 0x0 (0) Advanced Power Management Features (0x80000007/edx): TS: temperature sensing diode =3D true FID: frequency ID control =3D false VID: voltage ID control =3D false TTP: thermal trip =3D true TM: thermal monitor =3D true STC: software thermal control =3D false 100 MHz multiplier control =3D false hardware P-State control =3D true TscInvariant =3D true CPB: core performance boost =3D true read-only effective frequency interface =3D true processor feedback interface =3D false APM power reporting =3D false connected standby =3D true RAPL: running average power limit =3D true fast CPPC =3D false Physical Address and Linear Address Size (0x80000008/eax): maximum physical address bits =3D 0x34 (52) maximum linear (virtual) address bits =3D 0x39 (57) maximum guest physical address bits =3D 0x0 (0) Extended Feature Extensions ID (0x80000008/ebx): CLZERO instruction =3D true instructions retired count support =3D true always save/restore error pointers =3D true INVLPGB instruction =3D true RDPRU instruction =3D true memory bandwidth enforcement =3D true MCOMMIT instruction =3D false WBNOINVD instruction =3D true IBPB: indirect branch prediction barrier =3D true interruptible WBINVD, WBNOINVD =3D true IBRS: indirect branch restr speculation =3D true STIBP: 1 thr indirect branch predictor =3D true CPU prefers: IBRS always on =3D false CPU prefers: STIBP always on =3D true IBRS preferred over software solution =3D true IBRS provides same mode protection =3D true EFER[LMSLE] not supported =3D true INVLPGB supports TLB flush guest nested =3D true ppin processor id number supported =3D true SSBD: speculative store bypass disable =3D true virtualized SSBD =3D false SSBD fixed in hardware =3D false CPPC: collaborative processor perf ctrl =3D true PSFD: predictive store forward disable =3D true not vulnerable to branch type confusion =3D true IBPB_RET: ret addr predictor cleared =3D true branch sampling feature support =3D false (vuln to branch type confusion synth) =3D false Size Identifiers (0x80000008/ecx): number of threads =3D 0x20 (32) ApicIdCoreIdSize =3D 0x7 (7) performance time-stamp counter size =3D 40 bits (0) Feature Extended Size (0x80000008/edx): max page count for INVLPGB instruction =3D 0x7 (7) RDPRU instruction max input support =3D 0x1 (1) SVM Secure Virtual Machine (0x8000000a/eax): SvmRev: SVM revision =3D 0x1 (1) SVM Secure Virtual Machine (0x8000000a/edx): nested paging =3D true LBR virtualization =3D true SVM lock =3D true NRIP save =3D true MSR based TSC rate control =3D true VMCB clean bits support =3D true flush by ASID =3D true decode assists =3D true PMC virtualization =3D true SSSE3/SSE5 opcode set disable =3D false pause intercept filter =3D true pause filter threshold =3D true AVIC: AMD virtual interrupt controller =3D true virtualized VMLOAD/VMSAVE =3D true virtualized global interrupt flag (GIF) =3D true GMET: guest mode execute trap =3D true X2AVIC: virtualized X2APIC =3D true supervisor shadow stack =3D true guest Spec_ctl support =3D true ROGPT: read-only guest page table =3D true host MCE override =3D true INVLPGB/TLBSYNC hyperv interc enable =3D true VNMI: NMI virtualization =3D true IBS virtualization =3D true extended LVT AVIC access changes =3D true guest VMCB addr check =3D true bus lock threshold =3D true idle HLT intercept =3D true EXITINFO1 non-interceptible shutdown =3D true NASID: number of address space identifiers =3D 0x8000 (32768): L1 TLB information: 1G pages (0x80000019/eax): instruction # entries =3D 0x40 (64) instruction associativity =3D full (15) data # entries =3D 0x60 (96) data associativity =3D full (15) L2 TLB information: 1G pages (0x80000019/ebx): instruction # entries =3D 0x0 (0) instruction associativity =3D L2 off (0) data # entries =3D 0x20 (32) data associativity =3D 4 to 5-way (4) Performance Optimization Identifiers (0x8000001a/eax): 128-bit SSE executed full-width =3D false MOVU* better than MOVL*/MOVH* =3D true 256-bit SSE executed full-width =3D false 512-bit SSE executed full-width =3D true Instruction Based Sampling Identifiers (0x8000001b/eax): IBS feature flags valid =3D true IBS fetch sampling =3D true IBS execution sampling =3D true read write of op counter =3D true op counting mode =3D true branch target address reporting =3D true IbsOpCurCnt and IbsOpMaxCnt extend 7 =3D true invalid RIP indication support =3D true fused branch micro-op indication support =3D true IBS fetch control extended MSR support =3D true IBS op data 4 MSR support =3D false IBS L3 miss filtering support =3D true IBS load latency filtering support =3D true simplified DTLB page size & miss report =3D true Lightweight Profiling Capabilities: Availability (0x8000001c/eax): lightweight profiling =3D false LWPVAL instruction =3D false instruction retired event =3D false branch retired event =3D false DC miss event =3D false core clocks not halted event =3D false core reference clocks not halted event =3D false continuous mode sampling =3D false tsc in event record =3D false interrupt on threshold overflow =3D false Lightweight Profiling Capabilities: Supported (0x8000001c/edx): lightweight profiling =3D false LWPVAL instruction =3D false instruction retired event =3D false branch retired event =3D false DC miss event =3D false core clocks not halted event =3D false core reference clocks not halted event =3D false continuous mode sampling =3D false tsc in event record =3D false interrupt on threshold overflow =3D false Lightweight Profiling Capabilities (0x8000001c/ebx): LWPCB byte size =3D 0x0 (0) event record byte size =3D 0x0 (0) maximum EventId =3D 0x0 (0) EventInterval1 field offset =3D 0x0 (0) Lightweight Profiling Capabilities (0x8000001c/ecx): latency counter bit size =3D 0x0 (0) data cache miss address valid =3D false amount cache latency is rounded =3D 0x0 (0) LWP implementation version =3D 0x0 (0) event ring buffer size in records =3D 0x0 (0) branch prediction filtering =3D false IP filtering =3D false cache level filtering =3D false cache latency filteing =3D false Cache Properties (0x8000001d): --- cache 0 --- type =3D data (1) level =3D 0x1 (1) self-initializing =3D true fully associative =3D false extra cores sharing this cache =3D 0x0 (0) line size in bytes =3D 0x40 (64) physical line partitions =3D 0x1 (1) number of ways =3D 0xc (12) number of sets =3D 64 write-back invalidate =3D false cache inclusive of lower levels =3D false (synth size) =3D 49152 (48 KB) --- cache 1 --- type =3D instruction (2) level =3D 0x1 (1) self-initializing =3D true fully associative =3D false extra cores sharing this cache =3D 0x0 (0) line size in bytes =3D 0x40 (64) physical line partitions =3D 0x1 (1) number of ways =3D 0x8 (8) number of sets =3D 64 write-back invalidate =3D false cache inclusive of lower levels =3D false (synth size) =3D 32768 (32 KB) --- cache 2 --- type =3D unified (3) level =3D 0x2 (2) self-initializing =3D true fully associative =3D false extra cores sharing this cache =3D 0x0 (0) line size in bytes =3D 0x40 (64) physical line partitions =3D 0x1 (1) number of ways =3D 0x10 (16) number of sets =3D 1024 write-back invalidate =3D false cache inclusive of lower levels =3D true (synth size) =3D 1048576 (1024 KB) --- cache 3 --- type =3D unified (3) level =3D 0x3 (3) self-initializing =3D true fully associative =3D false extra cores sharing this cache =3D 0x3 (3) line size in bytes =3D 0x40 (64) physical line partitions =3D 0x1 (1) number of ways =3D 0x10 (16) number of sets =3D 32768 write-back invalidate =3D true cache inclusive of lower levels =3D false (synth size) =3D 33554432 (32 MB) extended APIC ID =3D 51 Core Identifiers (0x8000001e/ebx): core ID =3D 0x33 (51) threads per core =3D 0x1 (1) Node Identifiers (0x8000001e/ecx): node ID =3D 0x0 (0) nodes per processor =3D 0x1 (1) AMD Secure Encryption (0x8000001f): SME: secure memory encryption support =3D true SEV: secure encrypted virtualize support =3D true VM page flush MSR support =3D false SEV-ES: SEV encrypted state support =3D true SEV-SNP: SEV secure nested paging =3D true VMPL: VM permission levels =3D true RMPQUERY instruction support =3D true VMPL supervisor shadow stack support =3D true Secure TSC supported =3D true virtual TSC_AUX supported =3D true hardware cache coher across enc domains =3D true SEV guest exec only from 64-bit host =3D true restricted injection =3D true alternate injection =3D true full debug state swap for SEV-ES/SEV-SNP =3D true disallowing IBS use by host =3D true VTE: SEV virtual transparent encryption =3D true VMGEXIT parameter support =3D true virtual TOM MSR support =3D true IBS virtual support for SEV-ES/SEV-SNP =3D true PMC virtual support for SEV-ES/SEV-SNP =3D true RMPREAD instruction =3D true guest intercept control support =3D true segmented RMP support =3D true VMSA register protection support =3D true SMT protection support =3D true secure AVIC support =3D true allowed SEV features support =3D true SVSM communication page MSR support =3D false VIRT_RMPUPDATE & VIRT_PSMASH MSR support =3D false write to hypervisor in-used allowed =3D true IBPB on entry support =3D true encryption bit position in PTE =3D 0x33 (51) physical address space width reduction =3D 0x6 (6) number of VM permission levels =3D 0x4 (4) number of SEV-enabled guests supported =3D 0x3ee (1006) minimum SEV guest ASID =3D 0x1 (1) PQoS Extended Features (0x80000020): L3 bandwidth enforcement =3D true L3 slow memory bandwidth enforcement =3D true bandwidth monitoring event configuration =3D true L3 range reservation support =3D true assignable bandwidth monitoring counters =3D true SDCI allocation enforcement =3D true PQoS L3 Memory Bandwidth Enforcement (0x80000020/1): capacity bitmask length =3D 0xd (13) number of classes of service =3D 0xf (15) PQoS L3 Slow Memory Bandwidth Enforcement (0x80000020/2): capacity bitmask length =3D 0xd (13) number of classes of service =3D 0xf (15) PQoS Bandwidth Monitoring Event Configuration (0x80000020/3): number of bandwidth events available =3D 0x2 (2) reads to local NUMA =3D true reads to non-local NUMA =3D true non-temporal writes to local NUMA =3D true non-temporal writes to non-local NUMA =3D true reads to slow memory in local NUMA =3D true reads to slow memory in non-local NUMA =3D true dirty victims writes =3D true 0x80000020 0x04: eax=3D0x00000000 ebx=3D0x00000000 ecx=3D0x00000000 edx= =3D0x00000000 PQoS Assignable Bandwidth Monitoring Counters (0x80000020/5): QM_CTR counter size-24 =3D 0x14 (20) QM_CTR bit 61 is overflow =3D false (QM_CTR counter size) =3D 44 maximum supported ABCM counter ID =3D 0x1f (31) can measure COS bandwidth =3D true 0x80000020 0x06: eax=3D0x00000000 ebx=3D0x00000000 ecx=3D0x00000000 edx= =3D0x00000000 Extended Feature 2 (0x80000021): no nested data-breakpoints =3D true FsGsKernelGsBaseNonSerializing =3D true LFENCE always serializing =3D true SMM paging configuration lock support =3D true null selector clears base =3D true upper address ignore support =3D true automatic IBRS =3D true SMM_CTL MSR not supported =3D true FSRS: fast short REP STOSB support =3D true FSRC: fast short REP CMPSB support =3D true prefetch control MSR support =3D true L2TLB sizes are multiples of 32 =3D true AMD enhanced REP MOVSB/STOSB =3D true reserves 0F 01/7 for AMD use =3D true CPUID disable for non-privileged =3D true enhanced predictive store forwarding =3D true fast short REP SCASB support =3D true IC PREFETCH support =3D true FP512 to FP256 downgrade support =3D true workload OS feedback support =3D false ret addr predictor security support =3D true guest: selective branch pred barrier =3D true guest: PRED_CMD[IBPB] flushes br predict =3D true unaffected by spec return stack overflow =3D false unaffected by SRSO at user-kernel bound =3D true BP_CFG can mitigate other SRSO cases =3D true microcode patch size =3D 14368 (0x3820) return addr predictor size =3D 64 (0x40) Extended Performance Monitoring and Debugging (0x80000022): AMD performance monitoring V2 =3D true AMD LBR V2 =3D true AMD LBR stack & PMC freezing =3D true number of core perf ctrs =3D 0x6 (6) number of LBR stack entries =3D 0x10 (16) number of avail Northbridge perf ctrs =3D 0x10 (16) number of available UMC PMCs =3D 0x20 (32) active UMCs bitmask =3D 0x6db Multi-Key Encrypted Memory Capabilities (0x80000023): secure host multi-key memory support =3D true number of encryption key IDs =3D 0x3f (63) 0x80000024 0x00: eax=3D0x00000000 ebx=3D0x00000000 ecx=3D0x00000000 edx= =3D0x00000000 Segmented RMP Table (0x80000025): RMP segment size minimum supported =3D 0x24 (36) RMP segment size maximum supported =3D 0x2a (42) cacheable RMP segment definitions =3D 0x10 (16) cached segments hard limit =3D false AMD Extended CPU Topology (0x80000026): extended APIC ID =3D 51 --- level 0 --- level number =3D 0x0 (0) level type =3D core (1) bit width of level =3D 0x0 (0) power efficiency ranking available =3D false cores heterogeneous at this level =3D false components have varying number of cores =3D false number of logical processors at level =3D 0x1 (1) 0x80000027 0x00: eax=3D0x00000003 ebx=3D0x00000000 ecx=3D0x00000000 edx= =3D0x00000000 0x80000028 0x00: eax=3D0x00000000 ebx=3D0x00000000 ecx=3D0x00000000 edx= =3D0x00000000 (instruction supported synth): CMPXCHG8B =3D true conditional move/compare =3D true PREFETCH/PREFETCHW =3D true (multi-processing synth) =3D multi-core (c=3D32) (multi-processing method) =3D AMD leaf 0xb (APIC widths synth): CORE_width=3D7 SMT_width=3D0 (APIC synth): PKG_ID=3D0 CORE_ID=3D51 SMT_ID=3D0 (uarch synth) =3D AMD Zen 5, TSMC N4P (synth) =3D AMD EPYC (5th Gen) (Turin C1) [Zen 5], TSMC N4P --=20 You are receiving this mail because: You are the assignee for the bug.=