From owner-freebsd-hackers Mon Mar 20 09:42:20 1995 Return-Path: hackers-owner Received: (from majordom@localhost) by freefall.cdrom.com (8.6.10/8.6.6) id JAA01062 for hackers-outgoing; Mon, 20 Mar 1995 09:42:20 -0800 Received: from cs.weber.edu (cs.weber.edu [137.190.16.16]) by freefall.cdrom.com (8.6.10/8.6.6) with SMTP id JAA01056 for ; Mon, 20 Mar 1995 09:42:17 -0800 Received: by cs.weber.edu (4.1/SMI-4.1.1) id AA02256; Mon, 20 Mar 95 10:35:37 MST From: terry@cs.weber.edu (Terry Lambert) Message-Id: <9503201735.AA02256@cs.weber.edu> Subject: Re: SMP work To: rgrimes@gndrsh.aac.dev.com (Rodney W. Grimes) Date: Mon, 20 Mar 95 10:35:36 MST Cc: dufault@hda.com, hackers@freefall.cdrom.com In-Reply-To: <199503182206.OAA22038@gndrsh.aac.dev.com> from "Rodney W. Grimes" at Mar 18, 95 02:06:04 pm X-Mailer: ELM [version 2.4dev PL52] Sender: hackers-owner@FreeBSD.org Precedence: bulk > I think that the locking model to be used should be discussed amongst > us, as there are several alternatives. I have no firm opinions on this > issue. There are two books I recommend for a discussion of the locking model: UNIX Systems for Modern Architectures -- Schimmel The Magic Garden Explained There's a third one coming out from Prentice Hall called (tentatively) "UNIX Internals: The New Frontier". I don't have a release date on it yet. > It wouldn't be SMP if they had separate buses now would it :-). The > ISA/EISA/PCI buses and cache and memory are shared by 2 CPU chips. Actually, you can do loosely coupled SMP using a PCI/PCI bridge, per the standards. I don't know if anyone had built a board that could handle this yet. > These APIC's can be used for sending Interter Processor Interrupts, > that is how you start the second CPU up. They also allow you to control > which CPU gets which interrupts. You can prefer certain interrupts to > certain CPU's or you can have it dispatch the interrupt to the lowest > priority CPU, etc etc.. Since the APIC is built into the CPU the you > don't have the high I/O latency of talking to things like 8259's to > control them. On the other hand, it's two bus cycles instead of one for a grant with this type of arbitration. On the third hand (8-).), single cycle arbitration requires the use of ASICs that limit the number of processers you can use without geometrically increasing the amount of arbitration circuitry in your ASIC. > There is a paper on the Intel MP spec on ftp.intel.com. The file > name is mpspec.ps, but I forget what directory it is in. I have found this file to be corrupt. Intel will mail you the spec and it will only take a couple of days if you call their 800 number for their doc department. Or they may have fixed the file once I reported it to their FTP person. Terry Lambert terry@cs.weber.edu --- Any opinions in this posting are my own and not those of my present or previous employers.