Date: Sat, 19 Sep 2020 22:37:46 +0000 (UTC) From: Hans Petter Selasky <hselasky@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r365918 - head/sys/dev/usb/controller Message-ID: <202009192237.08JMbkjK048550@repo.freebsd.org>
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Author: hselasky Date: Sat Sep 19 22:37:45 2020 New Revision: 365918 URL: https://svnweb.freebsd.org/changeset/base/365918 Log: Fix for use of the XHCI driver on Cortex-A72 by adding a missing cache flush operation before writing to the XHCI_ERSTBA_LO/HI register(s). PR: 237666 Discussed with: Mark Millard <marklmi@yahoo.com> MFC after: 1 week Sponsored by: Mellanox Technologies // Nvidia Modified: head/sys/dev/usb/controller/xhci.c Modified: head/sys/dev/usb/controller/xhci.c ============================================================================== --- head/sys/dev/usb/controller/xhci.c Sat Sep 19 20:46:56 2020 (r365917) +++ head/sys/dev/usb/controller/xhci.c Sat Sep 19 22:37:45 2020 (r365918) @@ -432,6 +432,19 @@ xhci_start_controller(struct xhci_softc *sc) phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr); phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS); + /* + * PR 237666: + * + * According to the XHCI specification, the XWRITE4's to + * XHCI_ERSTBA_LO and _HI lead to the XHCI to copy the + * qwEvrsTablePtr and dwEvrsTableSize values above at that + * time, as the XHCI initializes its event ring support. This + * is before the event ring starts to pay attention to the + * RUN/STOP bit. Thus, make sure the values are observable to + * the XHCI before that point. + */ + usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc); + DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr); XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
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