From owner-freebsd-arch Wed Aug 22 1:28: 5 2001 Delivered-To: freebsd-arch@freebsd.org Received: from peter3.wemm.org (c1315225-a.plstn1.sfba.home.com [24.14.150.180]) by hub.freebsd.org (Postfix) with ESMTP id 495DF37B40E; Wed, 22 Aug 2001 01:27:50 -0700 (PDT) (envelope-from peter@wemm.org) Received: from overcee.netplex.com.au (overcee.wemm.org [10.0.0.3]) by peter3.wemm.org (8.11.0/8.11.0) with ESMTP id f7M8RoM78007; Wed, 22 Aug 2001 01:27:50 -0700 (PDT) (envelope-from peter@wemm.org) Received: from wemm.org (localhost [127.0.0.1]) by overcee.netplex.com.au (Postfix) with ESMTP id ED86038FD; Wed, 22 Aug 2001 01:27:49 -0700 (PDT) (envelope-from peter@wemm.org) X-Mailer: exmh version 2.3.1 01/18/2001 with nmh-1.0.4 To: tlambert2@mindspring.com Cc: Mitsuru IWASAKI , arch@FreeBSD.ORG, audit@FreeBSD.ORG, kumabu@t3.rim.or.jp Subject: Re: CFR: Timing to enable CR4.PGE bit In-Reply-To: <3B836737.9C15EA8@mindspring.com> Date: Wed, 22 Aug 2001 01:27:49 -0700 From: Peter Wemm Message-Id: <20010822082749.ED86038FD@overcee.netplex.com.au> Sender: owner-freebsd-arch@FreeBSD.ORG Precedence: bulk List-ID: List-Archive: (Web Archive) List-Help: (List Instructions) List-Subscribe: List-Unsubscribe: X-Loop: FreeBSD.ORG Terry Lambert wrote: > Peter Wemm wrote: > > Terry Lambert wrote: > > > Mitsuru IWASAKI wrote: > > > > > This part is fine. > > > > > > > > OK, I'll commit this one first. > > > > > > What does setting PGE early do for you? > > > > The change is to avoid violating the rules in the CPU developers > > guide. Did you read the thread? > > Yes. I still don't get what rules are being broken (no one > quoted anything in comments inline in the code, citing the > relevent pages in the guide, with a URL for the guide, for > example). > > Let me ask again: what was broken before that is now fixed? The very first article in the thread said: ======== According to developer's manual from Intel site, ftp://download.intel.com/design/PentiumII/manuals/24319202.pdf ---- 2.5. CONTROL REGISTERS [snip] PGE (2-17) Page Global Enable (bit 7 of CR4). (Introduced in the P6 family processors.) Enables the global page feature when set; disables the global page feature when clear. [snip] In addition, the bit must not ^^^^^^^^^^^^^^^^ be enabled before paging is enabled via CR0.PG. Program correctness ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ may be affected by reversing this sequence, and processor performance will be impacted. ---- Currently, we enable CR4.PGE bit in create_pagetables, then enable CR0.PG in locore.s. This seems to violate Intel's note. ====== This was in: Message-id: <20010809035801V.iwasaki@jp.FreeBSD.org> Subject: CFR: Timing to enable CR4.PGE bit From: Mitsuru IWASAKI Date: Thu, 09 Aug 2001 03:58:01 +0900 To: arch@FreeBSD.ORG Cc: audit@FreeBSD.ORG, kumabu@t3.rim.or.jp .. which is why I asked if you read the entire thread. I thought that quote was quite clear that we were in violation. Cheers, -Peter -- Peter Wemm - peter@FreeBSD.org; peter@yahoo-inc.com; peter@netplex.com.au "All of this is for nothing if we don't go to the stars" - JMS/B5 To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-arch" in the body of the message