From owner-svn-src-projects@freebsd.org Wed Aug 24 03:44:21 2016 Return-Path: Delivered-To: svn-src-projects@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id E6EAABC2C11 for ; Wed, 24 Aug 2016 03:44:21 +0000 (UTC) (envelope-from nwhitehorn@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 9B5C91A43; Wed, 24 Aug 2016 03:44:21 +0000 (UTC) (envelope-from nwhitehorn@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id u7O3iKbs016511; Wed, 24 Aug 2016 03:44:20 GMT (envelope-from nwhitehorn@FreeBSD.org) Received: (from nwhitehorn@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id u7O3iKZ0016508; Wed, 24 Aug 2016 03:44:20 GMT (envelope-from nwhitehorn@FreeBSD.org) Message-Id: <201608240344.u7O3iKZ0016508@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: nwhitehorn set sender to nwhitehorn@FreeBSD.org using -f From: Nathan Whitehorn Date: Wed, 24 Aug 2016 03:44:20 +0000 (UTC) To: src-committers@freebsd.org, svn-src-projects@freebsd.org Subject: svn commit: r304726 - in projects/powernv/powerpc: powerpc pseries X-SVN-Group: projects MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-projects@freebsd.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: "SVN commit messages for the src " projects" tree" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 24 Aug 2016 03:44:22 -0000 Author: nwhitehorn Date: Wed Aug 24 03:44:20 2016 New Revision: 304726 URL: https://svnweb.freebsd.org/changeset/base/304726 Log: Fix some SMP issues: - Use low thread priority in the wait loop for APs - Add more head room for XICS in its interrupt range: it uses 2^24 + 1 IRQs - OPAL doesn't like binding fictional interrupts (IPIs) to a particular CPU. Don't do that. Modified: projects/powernv/powerpc/powerpc/intr_machdep.c projects/powernv/powerpc/powerpc/mp_machdep.c projects/powernv/powerpc/pseries/xics.c Modified: projects/powernv/powerpc/powerpc/intr_machdep.c ============================================================================== --- projects/powernv/powerpc/powerpc/intr_machdep.c Wed Aug 24 03:44:16 2016 (r304725) +++ projects/powernv/powerpc/powerpc/intr_machdep.c Wed Aug 24 03:44:20 2016 (r304726) @@ -387,7 +387,7 @@ powerpc_get_irq(uint32_t node, u_int pin piclist[idx].irqs = 124; piclist[idx].ipis = 4; piclist[idx].base = nirqs; - nirqs += (1 << 24); + nirqs += (1 << 25); npics++; KASSERT(npics < MAX_PICS, Modified: projects/powernv/powerpc/powerpc/mp_machdep.c ============================================================================== --- projects/powernv/powerpc/powerpc/mp_machdep.c Wed Aug 24 03:44:16 2016 (r304725) +++ projects/powernv/powerpc/powerpc/mp_machdep.c Wed Aug 24 03:44:20 2016 (r304726) @@ -78,7 +78,8 @@ machdep_ap_bootstrap(void) __asm __volatile("msync; isync"); while (ap_letgo == 0) - ; + __asm __volatile("or 27,27,27"); + __asm __volatile("or 6,6,6"); /* Initialize DEC and TB, sync with the BSP values */ platform_smp_timebase_sync(ap_timebase, 1); Modified: projects/powernv/powerpc/pseries/xics.c ============================================================================== --- projects/powernv/powerpc/pseries/xics.c Wed Aug 24 03:44:16 2016 (r304725) +++ projects/powernv/powerpc/pseries/xics.c Wed Aug 24 03:44:20 2016 (r304726) @@ -250,6 +250,10 @@ xicp_bind(device_t dev, u_int irq, cpuse cell_t status, cpu; int ncpus, i, error; + /* Ignore IPIs */ + if (irq == MAX_XICP_IRQS) + return; + /* * This doesn't appear to actually support affinity groups, so pick a * random CPU. @@ -338,7 +342,6 @@ xicp_dispatch(device_t dev, struct trapf break; } -//printf("Interrupt %ld\n", xirr); KASSERT(i < sc->nintvecs, ("Unmapped XIRR")); powerpc_dispatch_intr(sc->intvecs[i].vector, tf); }