From owner-svn-src-head@freebsd.org Sun Aug 9 07:45:16 2015 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 65B0A99DCC0; Sun, 9 Aug 2015 07:45:16 +0000 (UTC) (envelope-from alc@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 49CDB7F8; Sun, 9 Aug 2015 07:45:16 +0000 (UTC) (envelope-from alc@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.70]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id t797jGRL032396; Sun, 9 Aug 2015 07:45:16 GMT (envelope-from alc@FreeBSD.org) Received: (from alc@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id t797jGWt032395; Sun, 9 Aug 2015 07:45:16 GMT (envelope-from alc@FreeBSD.org) Message-Id: <201508090745.t797jGWt032395@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: alc set sender to alc@FreeBSD.org using -f From: Alan Cox Date: Sun, 9 Aug 2015 07:45:16 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r286513 - head/share/man/man9 X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 09 Aug 2015 07:45:16 -0000 Author: alc Date: Sun Aug 9 07:45:15 2015 New Revision: 286513 URL: https://svnweb.freebsd.org/changeset/base/286513 Log: Revise the text about the atomicity of the defined operations across multiple processors. In particular, clearly state that the operations are always atomic when they are applied to the default memory type that is used by the kernel (and applications). Reviewed by: kib, jhb (an earlier version) MFC after: 1 week Modified: head/share/man/man9/atomic.9 Modified: head/share/man/man9/atomic.9 ============================================================================== --- head/share/man/man9/atomic.9 Sun Aug 9 06:58:06 2015 (r286512) +++ head/share/man/man9/atomic.9 Sun Aug 9 07:45:15 2015 (r286513) @@ -23,7 +23,7 @@ .\" .\" $FreeBSD$ .\" -.Dd June 20, 2015 +.Dd August 9, 2015 .Dt ATOMIC 9 .Os .Sh NAME @@ -67,8 +67,8 @@ .Ft int .Fn atomic_testandset_ "volatile *p" "u_int v" .Sh DESCRIPTION -Each of the atomic operations is guaranteed to be atomic in the presence of -interrupts. +Each of the atomic operations is guaranteed to be atomic across multiple +processors and in the presence of interrupts. They can be used to implement reference counts or as building blocks for more advanced synchronization primitives such as mutexes. .Ss Types @@ -162,17 +162,21 @@ guarantee that the lock is held before a Finally, one would use a write barrier when releasing the lock to ensure that all of the protected operations are completed before the lock is released. .Ss Multiple Processors -The current set of atomic operations do not necessarily guarantee atomicity -across multiple processors. -To guarantee atomicity across processors, not only does the individual -operation need to be atomic on the processor performing the operation, but -the result of the operation needs to be pushed out to stable storage and the -caches of all other processors on the system need to invalidate any cache -lines that include the affected memory region. -On the +In multiprocessor systems, the atomicity of the atomic operations on memory +depends on support for cache coherence in the underlying architecture. +In general, cache coherence on the default memory type, +.Dv VM_MEMATTR_DEFAULT , +is guaranteed by all architectures that are supported by +.Fx . +For example, cache coherence is guaranteed on write-back memory by the +.Tn amd64 +and .Tn i386 -architecture, the cache coherency model requires that the hardware perform -this task, thus the atomic operations are atomic across multiple processors. +architectures. +However, on some architectures, cache coherence may not be enabled on all +memory types. +To determine if cache coherence is enabled for a non-default memory type, +consult the architecture's documentation. .Ss Semantics This section describes the semantics of each operation using a C like notation. .Bl -hang